Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 12

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Table 16 •
Tx Registers
Following is a detailed definition of cpu_add [3:2]
decoding and an explanation of the Data Register,
Pattern RAM, Control Register, and Status Register.
Table 17 •
Table 18 •
Table 19 •
1 2
Bit
7:0
Bit
31:0
Bit
0
1
2
3
Bit
0
1
2
ARINC 429 Bus Interface
Enable 32
Rx Label Memory Register
Tx Data Register
Tx Control Register
Tx Status Register
programmed level
FIFO half full or
FIFO empty
Function
Function
Function
Loopback
Data rate
FIFO full
Parity
Label
nd
Function
bit as parity
Data
Reset State
Reset State
Reset State
0
0
0
0
0
0
0
0
Reset State
0
Type
R/W
Type
Type
R/W
R/W
R/W
R/W
v5.0
R
R
R
Address Map
00 – Data Register
01 – Control Register
10 – Status Register
11 – Unused
Read/Write Labels
Data rate: 0 = 100Kb/s; 1 = 12.5 or 50 Kbps
0 = Disable loopback; 1 = Enable loopback
0 = 32
Parity: 0 = odd; 1 = even
0 = not empty; 1 = empty
0 = Less than half full or programmed level; 1 = Half full
or programmed level
0 = not full; 1 = full
nd
Type
W
bit is data; 1 = 32
Description
Description
Description
nd
bit is parity
Description
Write Data