Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 8

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Core Parameters
Core429 has several top-level Verilog parameters (VHDL
generics) that are used to select the number of channels
and FIFO sizes of the core that is implemented. Using
these parameters allows the size of the core to be
reduced when all the channels are not required.
Table 7 •
I/O Signal Descriptions
ARINC Interface
Table 8 •
8
Parameter Name
CLK_FREQ
CPU_DATA_WIDTH
RXN
TXN
LEGACY_MODE
LABEL_SIZE_i
RX_FIFO_DEPTH_j
RX_FIFO_LEVEL_k
TX_FIFO_DEPTH_l
TX_FIFO_LEVEL_m
TXRXSPEED_n
Note: Where i, j, k, l, m, and n are from 0 to 15.
Name
clk
reset_n
txa [TXN-1:0]
txb [TXN-1:0]
rxa [RXN-1:0]
rxb [RXN-1:0]
ARINC 429 Bus Interface
FIFO and Label Parameters
Clock and Reset
Clock Frequency
CPU Data Bus Width
Rx Channels
Tx Channels
0 = Normal mode; 1 = Legacy mode
Number of Labels for Rx Channel i
Depth of FIFO for Rx Channel j ARINC word
FIFO Level for Rx Channel k
Depth of FIFO for Tx Channel l ARINC word
FIFO Level for Tx Channel m
When this parameter is set to '1', a bit rate of 100/50 kbps is
selected. Otherwise selects a bit rate of 100/12.5 kbps. The bit
rate can be changed for the Rx/Tx channel pair. Refer to the Tx
and Rx control register bit descriptions in
and
Table 18 on page
Type
Out
Out
In
In
In
In
12.
Description
Master clock input (1, 10, 16, or 20 Mhz)
Active low asynchronous reset
ARINC transmit output A
ARINC transmit output B
ARINC receiver input A
ARINC receiver input B
v5.0
Table 14 on page 11
For RTL versions, the parameters in
directly set. For netlist versions of the core, a netlist
implementing four Tx and four Rx channels is provided
as per the defaults above. Actel will supply netlists with
alternative parameter settings on request.
Description
1, 10, 16, 20 MHz
8, 16, 32 bits
1 to 16
1 to 16
0,1
1 to 256
32, 64, 128, 256, 512
1 to 64
32, 64, 128, 256, 512
1 to 64
0, 1
Allowed Values
Table 7
Default
1 MHz
64
32
16
32
16
can be
8
4
4
0
0