Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 20

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

List of Changes
The following table lists critical changes that were made in the current version of the document.
2 0
Previous Version Changes in Current Version (v 5 .0 )
ARINC 429 Bus Interface
v4.1
The
Figure 2
The
A paragraph was added to the end of the
Table 6
Figure 3
The
The
The
Table 7
The first four rows of
signal, modify the int_out_tx signal description, and add the rx_fifo_full through tx_fifo_empty
signals. The "Clock and Reset" section was renamed to
Interface" section was renamed to
Table 11
Information about the Tx module was added to the
The channel decoding values were updated for the 32-bit CPU data bus in the
Operation"
The Address Map was updated in the
Table 14
10 descriptions. Label memory address was renamed reload label memory, and its description was
updated.
Table 15
description was modified.
Table 16
Table 18
Table 19
FIFO half full or programmed level, and its type and description were modified.
The
Information was added to the
Table 20
ARINC bit 10, match ARINC bit 9, transmitter data rate, and transmitter data rate.
Table 21
The signal names cpu_clk and cpu_addr[7:0] were changed to clk and cpu_add[8:0] in
through
and notes were added to each figure.
"Key Features" section
"General Description" section
"Default Mode" section
"Functional Description" section
"Legacy Mode" section
"Label Memory Operation" section
was updated to add Fusion.
was updated to add the TXRXSPEED_n parameter, and the table note was updated.
was added.
was updated.
Figure
was moved to a later position in the document, just before the
was updated to rename Data to Label and update the type and description.
was updated to modify the data rate description.
was updated to modify the type of FIFO empty and FIFO full. FIFO half full was renamed to
was updated to change the type from R/W to R for all bits.
was updated to modify the data rate, decoder, match header bit 9, and match header bit
was updated to modify the description for receiver 1 data rate, label compare, match
was updated to rename FIFO half full to FIFO half full or programmed level, and the
section.
12. The wave forms were modified in
Table 9
was updated to modify the selectable data rate on each channel.
was added.
was added.
"Legacy Operation" section
were moved to
and
"Default Mode
was updated.
"Rx Registers" section
"ARINC 429 Overview" section
was added.
v5.0
"Core429 Device Requirements"
Table
Signals".
"Legacy Interface"
8.
Figure
Table 9
to clarify its purpose and configurability.
7,
and the
"ARINC Interface"
Figure
was updated to remove the tx_en
"Tx Registers"
10,
were updated.
section.
"Default Mode"
Figure
section.
11, and
and the "ARINC
"Default Mode
section.
Figure
section.
Figure 7
12,
11,
16–17
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