Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 2

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

Contents
General Description
Core429 provides a complete Transmitter (Tx) and
Receiver (Rx). A typical system implementation using
Core429 is shown in
The core consists of three main blocks: Transmit, Receive,
and
connection to an external CPU. The CPU interface
configures the transmit and receive control registers and
initializes the label memory. The core interfaces to the
ARINC 429 bus through an external ARINC 429 line driver
and line receiver. A detailed description of the Rx
interface and Tx interface is provided in the
Description" section on page
External Components
There are two external components required for proper
operation of Core429:
2
General Description .................................................... 2
ARINC 429 Overview .................................................. 2
Core429 Device Requirements ................................... 3
Memory Requirements ............................................... 4
Core429 Overview ...................................................... 5
Default Mode ............................................................. 5
Functional Description ............................................... 5
Legacy Mode ............................................................... 7
Core Parameters ......................................................... 8
I/O Signal Descriptions ............................................... 8
Default Mode Operation ......................................... 10
Legacy Operation ..................................................... 13
Status Register .......................................................... 15
CPU Interface Timing for Default Mode ................. 16
Clock Requirements .................................................. 17
Core429 Verification ................................................ 17
Testbench .................................................................. 17
Line Drivers ............................................................... 18
Line Receivers ........................................................... 18
Loopback Interface ................................................... 18
Development System ................................................ 18
Ordering Information .............................................. 19
List of Changes ......................................................... 20
Datasheet Categories ............................................... 21
ARINC 429 Bus Interface
• Standard ARINC 429 line driver
• Standard ARINC 429 line receiver
CPU
Interface
Figure
(Figure
1.
5.
1).
Core429
"Functional
requires
v5.0
Figure 1 •
ARINC 429 Overview
ARINC 429 is a two-wire, point-to-point data bus that is
application-specific
aircraft. The connection wires are twisted pairs. Words
are 32 bits in length and most messages consist of a
single data word. The specification defines the electrical
standard and data characteristics and protocols.
ARINC 429 uses a unidirectional data bus standard (Tx
and Rx are on separate ports) known as the Mark 33
Digital Information Transfer System (DITS). Messages are
transmitted at 12.5, 50 (optional), or 100 kbps to other
system elements that are monitoring the bus messages.
The transmitter is always transmitting either 32-bit data
words or the Null state.
The ARINC standard supports High, Low, and Null states
(Figure
transmitted between ARINC words. No more than 20
receivers can be connected to a single bus (wire pair) and
no less than one receiver, though there will normally be
more.
Figure 2 •
Figure 3 on page 3
data.
Each ARINC word contains five fields:
CPU
B
A
• Parity
Low
Low
High
Null
High
Null
2). A minimum of four Null bits should be
+5
–5
+5
–5
0
0
1
1
Glue
Logic
Typical Core429 System—One Tx and One Rx
ARINC Standard
2
0
3
1
CPU
Interface
1
4
shows the bit positions of ARINC
for
CoreARINC429
5
Actel FPGA
0
commercial
6
1
7
0
8
1
Rx I/F
Tx I/F
9 10
0
0
and
32
1
transport
"A" Leg
"B" Leg
Bit
Number
Data
TxHi
TxLo
RxHi
RxLo