Core429-DEV-KIT Actel, Core429-DEV-KIT Datasheet - Page 11

• Manufacturer Part Number: Core429-DEV-KIT
• Description: MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
• Manufacturer: Actel

Specifications of Core429-DEV-KIT

• Processor To Be Evaluated: ProASIC Plus
• Interface Type: RS-232

The address bit 4 is used to determine Rx/Tx as follows:
The address bits 5, 6, 7, and 8 are used for decoding the
16 channels as follows:
Table 12 •
Register Definitions
Rx Registers
Following is the detailed definition of cpu_add [3:2]
decoding and the explanation of Data Register, Control
Register, Status Register, and Label Memory Register
(Table 13
Table 13 •
Table 14 •
Table 15 •
Bit
31:0
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
0 – Rx
1 – Tx
0000 – Channel0
MSB
8
through
Enable 32
Reload label memory
CPU Address Bit Positions
Rx Data Register
Rx Control Register
Rx Status Register
Match header bit 10
Match header bit 9
programmed level
Label recognition
FIFO half full or
FIFO empty
Channel Number
Function
Function
Data rate
Table 16 on page
Decoder
FIFO full
7
Parity
nd
bit as parity
Function
Data
6
Reset State
Reset State
12).
0
0
0
0
0
0
0
0
0
0
0
5
Reset State
9-Bit CPU Address
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Tx/Rx
R
R
R
v5.0
4
Table 12
Address Map
0001 – Channel1
1110 – Channel14
1111 – Channel15
00 – Data Register
01 – Control Register
10 – Status Register
11 – Label Memory
0 = not empty; 1 = empty
0 = Less than programmed level; 1 = FIFO is filled at least up
to programmed level
0 = not full; 1 = full
.
.
Data rate: 0 = 100Kb/s; 1 = 12.5 or 50 Kbps
Label compare: 0 = disable; 1 = enable
0 = 32
Parity: 0 = odd; 1 = even
0: SDI bit comparison disabled;
1: SDI bit comparison enabled; ARINC bits 9 and 10 must
match bits 5 and 6 respectively.
If bit 4 is set then this bit should match the ARINC header
bit 9 (SDI bit).
If bit 4 is set then this bit should match the ARINC header
bit 10 (SDI bit).
When bit 7 is set to '1', label memory address pointers are
initialized to '000'. Set this bit to change the contents of
the label memory.
shows the CPU address bit information.
Register Index
3
nd
Type
.
.
bit is data; 1 = 32
R
2
Description
Description
nd
bit is parity
ARINC 429 Bus Interface
Description
Read Data
1
Byte Index
LSB
0
11