EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 10

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

ADuC7060
SPI Timing
Table 3. SPI Master Mode Timing (Phase Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
Table 4. SPI Master Mode Timing (Phase Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
t
t
HCLK
UCLK
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL before the clock divider.
depends on the clock divider or CD bits in PLLCON MMR. t
= 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
1
1
t
1
1
DAV
t
SH
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
t
DSU
HCLK
HCLK
MSB IN
= t
= t
t
DHD
UCLK
UCLK
2
MSB
2
t
SL
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2
2
CD
CD
.
t
.
DF
Min
1 × t
2 × t
t
DR
BITS 6 TO 1
UCLK
UCLK
BITS 6 TO 1
Min
1 × t
2 × t
UCLK
UCLK
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
30
30
30
30
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
30
30
30
30
LSB IN
t
SF
HCLK
HCLK
LSB
HCLK
HCLK
Max
25
90
40
40
40
40
Max
25
40
40
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns