EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 31

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Power and Clock Control Registers
Name:
Address:
Default value:
Access:
Function:
Table 30. POWCON0 MMR Bit Designations
Bit
7
6
5
4
3
2 to 0
Table 31. ADuC7060 Power Saving Modes
POWCON0[6:3]
1111
1110
1100
1000
0000
Name
Reserved
XPD
PLLPD
PPD
COREPD
CD[2:0]
POWKEY1
0xFFFF0404
0xXXXX
When writing to POWCON0, the value of
0x01 must be written to this register in the
instruction immediately before writing to
POWCON0.
Write
Mode
Active
Pause
Nap
Sleep
Stop
Description
This bit must always be set to 0.
XTAL power-down.
Cleared by user to power down the external crystal circuitry.
Set by user to enable the external crystal circuitry.
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active
clock source remain in normal power mode.
This bit is cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are
enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
Peripherals power-down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; Bit 3 and
Bit 4 must be cleared simultaneously.
Set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer1) can remain active.
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down
command is written to POWCON0.
Cleared to power down the ARM core.
Set by default and set by hardware on a wake-up event.
Core clock depends on CD setting:
[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz
Core
Yes
Peripherals
Yes
Yes
PLL
Yes
Yes
Yes
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XTAL/T2/T3
Yes
Yes
Yes
Yes
Name:
Address:
Default value:
Access:
Function:
2
C and UART serial ports.
IRQ0 to IRQ3
Yes
Yes
Yes
Yes
Yes
POWCON0
0xFFFF0408
0x7B
Read and write
This register controls the clock divide bits
controlling the CPU clock (HCLK).
Start-Up/Power-On Time
130 ms at CD = 0
4.8 μs at CD = 0; 660 μs at CD = 7
4.8 μs at CD = 0; 660 μs at CD = 7
66 μs at CD = 0; 900 μs at CD = 7
66 μs at CD = 0; 900 μs at CD = 7
ADuC7060