EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 89

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Bit
3
2
1
0
I
Name:
Address:
Default value:
Access:
Function:
I
Name:
Address:
Default value:
Access:
Function:
2
2
C Slave Receive, I2CSRX, Register
C Slave Transmit, I2CSTX, Register
Name
I2CSRXQ
I2CSTXQ
I2CSTFE
I2CETSTA
I2CSRX
0xFFFF0930
0x00
Read only
This 8-bit MMR is the I
register.
I2CSTX
0xFFFF0934
0x00
Write only
This 8-bit MMR is the I
register.
Description
I
I
I
I
This bit is set to 1 when the receive FIFO of the slave is not empty. This bit causes an interrupt to occur if the
I2CSRXENI bit in I2CSCON is set.
The receive FIFO must be read or flushed to clear this bit.
This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CSCON
is =0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in
I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit
causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set.
This bit is cleared in all other conditions.
This bit goes high if the transmit FIFO is empty when a master requests data from the slave. This bit is asserted at
the rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
If the I2CSETEN bit in I2CSCON is =0, this bit goes high if the slave transmit FIFO is empty. If the I2CSETEN bit in
I2CSCON = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit
asserts once only for a transfer.
This bit is cleared after being read.
2
2
2
2
C slave receive request bit.
C slave transmit request bit.
C slave FIFO underflow status bit.
C slave early transmit FIFO status bit.
2
2
C slave receive
C slave transmit
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I
Name:
Address:
Default value:
Access:
Function:
I
Name:
Addresses:
Default value:
Access:
Function:
2
2
C Hardware General Call Recognition, I2CALT, Register
C Slave Device ID, I2CIDx, Registers
I2CALT
0xFFFF0938
0x00
Read and write
This 8-bit MMR is used with hardware general
calls when the I2CSCON Bit 3 is set to 1. This
register is used in cases where a master is
unable to generate an address for a slave and,
instead, the slave must generate the address for
the master.
I2CIDx
0xFFFF093C = I2CID0
0xFFFF0940 = I2CID1
0xFFFF0944 = I2CID2
0xFFFF0948 = I2CID3
0x00
Read and write
These 8-bit MMRs are programmed with the
I
Addresses section for further details.
2
C bus IDs of the slave. See the I
ADuC7060
2
C Bus