EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

ADuC7060
COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read
and write.
Table 16. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x001C
0x0020
0x0024
0x0028
0x0030
0x0034
0x0038
0x003C
0x0100
0x0104
0x0108
0x010C
0x011C
0x013C
Table 17. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
1
Updated by the kernel.
IRQSTAN
FIQSTAN
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
IRQBASE
IRQVEC
IRQP0
IRQP1
IRQP2
IRQCONN
IRQCONE
IRQCLRE
FIQSTA
FIQSIG
FIQEN
FIQCLR
FIQVEC
Name
REMAP
RSTSTA
RSTCLR
1
Byte
1
1
1
Access
Type
R/W
R/W
W
4
4
Byte
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
R
R/W
Access
Type
R
R
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
W
R
R/W
Default Value
0x00
0x01
0x00
Default
Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Rev. 0 | Page 24 of 100
Description
REMAP control register. See the Remap Operation section.
RSTSTA status MMR. See the Reset section.
RSTCLR MMR for clearing the RSTSTA register.
Description
Active IRQ source.
Current state of all IRQ sources (enabled and disabled).
Enabled IRQ sources.
MMR to disable IRQ sources.
Software interrupt configuration MMR.
Base address of all vectors. Points to the start of the 64-byte memory block,
which can contain up to 32 pointers to separate subroutine handlers.
This register contains the subroutine address for the currently active IRQ
source.
Contains the interrupt priority setting for interrupt Source 1 to Source 7.
An interrupt can have a priority setting of 0 to 7. For example:
Contains the interrupt priority setting for Interrupt Source 8 to Interrupt
Source 15. For example:
Contains the interrupt priority setting for Interrupt Source 16 to Interrupt
Source 19.
Used to enable IRQ and FIQ interrupt nesting.
Configures the external interrupt sources as rising edge, falling edge, or
level triggered.
Used to clear an edge-level-triggered interrupt source.
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
Active FIQ source.
Current state of all FIQ sources (enabled and disabled).
Enabled FIQ sources.
MMR to disable FIQ sources.
FIQ interrupt vector.
Indicates the priority level of an FIQ that has just caused an FIQ
exception.
Bits[7:4] contain the priority level for Interrupt 1.
Bits[11:8] contain the priority level for Interrupt 2.
Bits[31:28] contain the priority level for Interrupt 7.
Bits[7:4] contain the priority level for Interrupt 9.
Bits[11:8] contain the priority level for Interrupt 10.
Bits[31:28] contain the priority level for Interrupt 15.