EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Table 13. FEEMOD MMR Bit Designations
Bit
15:9
8
7:5
4
3
2:0
Table 14. Command Codes in FEECON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
The FEECON register always reads 0x07 immediately after execution of any of these commands.
1
1
1
1
1
1
1
Description
Reserved.
Reserved. Always set this bit to 0.
Reserved. Always set these bits to 0 except when
writing keys.
Flash/EE interrupt enable.
Set by user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt.
Erase/write command protection.
Set by user to enable the erase and write commands.
Cleared to protect the Flash against the erase/write
command.
Reserved. Always set these bits to 0.
Command
Null
Single read
Single write
Erase/write
Single verify
Single erase
Mass erase
Reserved
Reserved
Reserved
Reserved
Signature
Protect
Reserved
Reserved
Ping
Description
Idle state.
Load FEEDAT with the 16-bit data. Indexed by FEEADR.
Write FEEDAT at the address pointed by FEEADR. This operation takes 50 μs.
Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This operation takes
approximately 24 ms.
Compare the contents of the location pointed to by FEEADR to the data in FEEDAT. The result of the
comparison is returned in FEESTA Bit 1.
Erase the page indexed by FEEADR.
Erase 30 kB of user space. The 2 kB of kernel are protected. To prevent accidental execution, a command
sequence is required to execute this instruction. See the Command Sequence for Executing a Mass Erase
section.
Reserved.
Reserved.
Reserved.
Reserved.
This command results in a 24-bit LFSR-based signature being generated and loaded into FEESIGN MMR. This
operation takes 16,389 clock cycles.
This command can run only once. The value of FEEPRO is saved and removed only with a mass erase (0x06) or
the key.
Reserved.
Reserved.
No operation; interrupt generated.
Rev. 0 | Page 21 of 100
FEECON Register
FEECON is an 8-bit command register. The commands are
described in Table 14.
Name:
Address:
Default value:
Access:
FEECON
0xFFFF0E08
0x07
Read and write
ADuC7060