EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 43

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Bit
7
6 to 0
1
2
Table 44. ADC Conversion Rates and Settling Times
Chop
Enabled
No
No
No
No
Yes
1
Table 45. Allowable Combinations of SF and AF
SF
0 to 31
32 to 63
64 to 127
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
In low power mode and low power plus mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All f
by 4 (approximately).
An additional time of approximately 60 μs per ADC is required before the first ADC is available.
Name
NOTCH2
SF[6:0]
Averaging
Factor
No
No
Yes
Yes
N/A
Description
Sinc3 modify. Set by user to modify the standard sinc3 frequency response to increase the filter stop band rejection by
approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
where f
Sinc3 decimation factor (SF)
sinc3 filter. The output rate from the sinc3 filter is given by
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, f
For SF = 127, f
For information on calculating the f
f
f
NOTCH2
ADC
NOTCH
Running
Average
No
Yes
No
Yes
N/A
= (512,000/([SF+1] × 64)) Hz
0
Yes
Yes
Yes
= 1.333 × f
is the location of the first notch in the response.
ADC
ADC
is forced to 60 Hz.
is forced to 50 Hz.
f
[
[
[
[
[
ADC
SF
SF
SF
SF
SF
NOTCH
512
512
Normal Mode
+
+
+
+
+
] 1
] 1
] 1
,
] 1
,
] 1
000
000
512
512
×
×
×
×
×
1
512
.The value (SF) written in these bits controls the oversampling (decimation factor) of the
64
64
64
64
64
1 to 7
Yes
Yes
No
,
,
000
000
×
×
×
,
000
3 [
3 [ AF
3 [ AF
ADC
+
+
+
2
AF
for SF (other than 126 and 127) and AF values, refer to Table 44.
Rev. 0 | Page 43 of 100
]
]
]
+
3
8 to 63
Yes
No
No
f
[
[
[
[
[
ADC
SF
SF
SF
SF
SF
131
131
+
Low Power Mode
+
+
+
+
] 1
] 1
] 1
,
,
] 1
] 1
072
072
131
131
×
×
×
×
×
131
64
64
64
,
64
64
,
072
AF Range
072
×
×
×
,
072
3 [
[
3 [
3 AF
+
+
+
AF
AF
]
]
]
+
3
t
SETTLING
f
f
f
f
f
ADC
ADC
ADC
ADC
ADC
3
4
1
2
2
1
ADC
calculations should be divided
ADuC7060