EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 85

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

I
Name:
Address:
Default value:
Access:
Function:
I
Name:
Address:
Default value:
Access:
Function:
I
Name:
Address:
Default value:
Access:
Function:
Table 96. I2CMCNT0 MMR Bit Descriptions
Bit
15:9
8
7:0
2
2
2
C Master Receive, I2CMRX, Register
C Master Transmit, I2CMTX, Register
C Master Read Count, I2CMCNT0, Register
Name
I2CRECNT
I2CRCNT
I2CMRX
0xFFFF0908
0x00
Read only
This 8-bit MMR is the I
register.
I2CMTX
0xFFFF090C
0x00
Write only
This 8-bit MMR is the I
register.
I2CMCNT0
0xFFFF0910
0x0000
Read and write
This 16-bit MMR holds the required number
of bytes when the master begins a read
sequence from a slave device.
Description
Reserved.
Set this bit if more than 256 bytes are
required from the slave.
Clear this bit when reading 256 bytes or
fewer.
These eight bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required, set
these bits to 0.
2
2
C master receive
C master transmit
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I
Name:
Address:
Default value:
Access:
Function:
I
Name:
Address:
Default value:
Access:
Function:
Table 97. I2CADR0 MMR in 7-Bit Address Mode
Bit
7:1
0
Table 98. I2CADR0 MMR in 10-Bit Address Mode
Bit
7:3
2:1
0
2
2
C Master Current Read Count, I2CMCNT1, Register
C Address 0, I2CADR0, Register
Name
I2CADR
Name
R/ W
I2CMADR
R/ W
Description
These bits contain the 7-bit address of the
required slave device.
Bit 0 is the read/write bit.
I2CMCNT1
0xFFFF0914
0x00
Read only
This 8-bit MMR holds the number of bytes
received so far during a read sequence with a
slave device.
I2CADR0
0xFFFF0918
0x00
Read and write
This 8-bit MMR holds the 7-bit slave address
and the read/write bit when the master begins
communicating with a slave.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Description
These bits must be set to [11110b] in 10-bit
address mode.
These bits contain ADDR[9:8] in 10-bit
addressing mode.
Read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
ADuC7060