EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 46

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

ADuC7060
Table 50. ADC1OF MMR Bit Designations
Bits
15 to 0
Primary Channel ADC Gain Calibration Register
Name:
Address:
Default value:
Access:
Function:
Table 51. ADC0GN MMR Bit Designations
Bits
15 to 0
Auxiliary Channel Gain Calibration Register
Name:
Address:
Default value:
Access:
Function:
Description
ADC1 16-bit calibration offset value.
ADC0GN
0xFFFF052C
Part specific, factory programmed
Read and write
This gain MMR holds a 16-bit gain
calibration coefficient for scaling the primary
ADC conversion result. The register is
configured at power-on with a factory default
value. However, this register is automatically
overwritten if a gain calibration of the
primary ADC is initiated by the user via bits
in the ADCMDE MMR. User code can write
to this calibration register only if the ADC is
in idle mode. An ADC must be enabled and
in idle mode before being written to any
offset or gain register. The ADC must be in
idle mode for at least 23 μs.
Description
ADC0 16-bit calibration gain value.
ADC1GN
0xFFFF0530
Part specific, factory programmed
Read and write
This gain MMR holds a 16-bit gain calibra-
tion coefficient for scaling an auxiliary channel
conversion result. The register is configured
at power-on with a factory default value.
However, this register is automatically over-
written if a gain calibration of the auxiliary
channel is initiated by the user via bits in the
ADCMDE MMR. User code can only write to
this calibration register if the ADC is in idle
mode. An ADC must be enabled and in idle
mode before being written to any offset or gain
register. The ADC must be in idle mode for at
least 23 μs.
Rev. 0 | Page 46 of 100
Table 52. ADC1GN MMR Bit Designations
Bits
15 to 0
Primary Channel ADC Result Counter Limit Register
Name:
Address:
Default value:
Access:
Function:
Table 53. ADC0RCR MMR Bit Designations
Bits
15 to 0
Primary Channel ADC Result Count Register
Name:
Address:
Default value:
Access:
Function:
Table 54. ADC0RCV MMR Bit Designations
Bits
15 to 0
Description
ADC1 16-bit calibration gain value.
ADC0RCR
0xFFFF0534
0x0001
Read and write
This 16-bit MMR sets the number of
conversions required before an ADC
interrupt is generated. By default, this
register is set to 0x01. The ADC counter
function must be enabled via the ADC result
counter enable bit in the ADCCFG MMR.
Description
ADC0 result counter limit/reload register.
ADC0RCV
0xFFFF0538
0x0000
Read only
This 16-bit, read-only MMR holds the
current number of primary ADC conversion
results. It is used in conjunction with
ADC0RCR to mask primary channel ADC
interrupts, generating a lower interrupt rate.
When ADC0RCV = ADC0RCR, the value in
ADC0RCV resets to 0 and recommences
counting. It can also be used in conjunction
with the accumulator (ADC0ACC) to allow
an average calculation to be undertaken. The
result counter is enabled via ADCCFG[0].
This MMR is also reset to 0 when the
primary ADC is reconfigured, that is, when
the ADC0CON or ADCMDE is written.
Description
ADC0 result counter register.