EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 27

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Table 23. I
Address
0x0900
0x0904
0x0908
0x090C
0x0910
0x0914
0x0918
0x091C
0x0924
0x0928
0x092C
0x0930
0x0934
0x0938
0x093C
0x0940
0x0944
0x0948
0x094C
Table 24. SPI Base Address = 0xFFFF0A00
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Table 25. GPIO Base Address = 0xFFFF0D00
Address
0x0D00
0x0D04
0x0D08
0x0D20
0x0D24
0x0D28
0x0D2C
0x0D30
0x0D34
0x0D38
0x0D3C
0x0D40
0x0D44
0x0D48
0x0D4C
2
Name
I2CMCON
I2CMSTA
I2CMRX
I2CMTX
I2CMCNT0
I2CMCNT1
I2CADR0
I2CADR1
I2CDIV
I2CSCON
I2CSSTA
I2CSRX
I2CSTX
I2CALT
I2CID0
I2CID1
I2CID2
I2CID3
I2CFSTA
C Base Address = 0xFFFF0900
Name
GP0CON
GP1CON
GP2CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
GP2SET
GP2CLR
GP2PAR
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
Byte
2
2
1
1
2
1
1
1
2
2
2
1
1
1
1
1
1
1
2
Byte
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
R/W
R
R
W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
Byte
4
1
1
1
2
Access
Type
RW
RW
RW
RW
W
W
R/W
RW
W
W
R/W
RW
W
W
R/W
Default Value
0x00000000
0x00000000
0x00000000
0x000000XX
0x000000XX
0x000000XX
0x00000000
0x000000XX
0x000000XX
0x000000XX
0x00000000
0x000000XX
0x000000XX
0x000000XX
0x00000000
Default
Value
0x0000
0x0000
0x00
0x00
0x0000
0x00
0x00
0x00
0x1F1F
0x0000
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0000
R
R
W
W
R/W
Access Type
Description
I
I
I
I
I
register prior to reading from a slave device.
I
bytes already received during a read from slave sequence.
Address byte register. Write the required slave address here prior to
communications.
Address byte register. Write the required slave address here prior to
communications. Only used in 10-bit mode.
I
I
I
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 0 | Page 27 of 100
C master control register.
C master status register.
C master receive register.
C master transmit register.
C master read count register. Write the number of required bytes into this
C master current read count register. This register contains the number of
C clock control register. Used to configure the SCLK frequency.
C slave control register.
C slave status register.
C slave receive register.
C slave transmit register.
C hardware general call recognition register.
C Slave ID0 register. Slave bus ID register.
C Slave ID1 register. Slave bus ID register.
C Slave ID2 register. Slave bus ID register.
C Slave ID3 register. Slave bus ID register.
C FIFO status register. Used in both master and slave modes.
Description
GPIO Port 0 control MMR.
GPIO Port 1 control MMR.
GPIO Port 2 control MMR.
GPIO Port 0 data control MMR.
GPIO Port 0 data set MMR.
GPIO Port 0 data clear MMR.
GPIO Port 0 pull-up disable MMR.
GPIO Port 1 data control MMR.
GPIO Port 1 data set MMR.
GPIO Port 1 data clear MMR.
GPIO Port 1 pull-up disable MMR.
GPIO Port 2 data control MMR.
GPIO Port 2 data set MMR.
GPIO Port 2 data clear MMR.
GPIO Port 2 pull-up disable MMR.
0x00000000
0x00
0xXX
0x1B
0x0000
Default Value
Description
SPI status MMR.
SPI receive MMR.
SPI transmit MMR.
SPI baud rate select MMR.
SPI control MMR.
ADuC7060