EVAL-ADUC7060QSPZ Analog Devices Inc, EVAL-ADUC7060QSPZ Datasheet - Page 87

• Manufacturer Part Number: EVAL-ADUC7060QSPZ
• Description: Quick Start Development System
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCU, ARM7r

Specifications of EVAL-ADUC7060QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5189809

Table 101. I2CSCON MMR Bit Designations
Bit
15 to 11
10
9
8
7
6
5
4
3
2
1
0
Name
I2CSTXENI
I2CSRXENI
I2CSSENI
I2CNACKEN
I2CSSEN
I2CSETEN
I2CGCCLR
I2CHGCEN
I2CGCEN
Reserved
I2CSEN
Description
Reserved bits.
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this interrupt source.
I
Set this bit to no acknowledge the next byte in the transmission sequence.
Clear this bit to let the hardware control the acknowledge/no acknowledge sequence.
I
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
I
Writing a 1 to this bit clears the general call status and ID bits in the I2CSSTA register.
Clear this bit at all other times.
Hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00)
and a data byte, the device checks the contents of the I2CALT against the receive register. If the contents match,
the device has received a hardware general call. This is used if a device needs urgent attention from a master
device without knowing which master it needs to turn to. This is a “to whom it may concern” call. The ADuC7060
watches for these addresses. The device that requires attention embeds its own address into the message. All
masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the
I2CALT register should always be written to 1, as per the I
General call enable bit. Set this bit to enable the slave device to acknowledge an I
(write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave
address by hardware) as teh data byte, the I
command can be used to reset an entire I
address by hardware) as the data byte, teh general call interrupt status bit sets on any general call. The user must
take corrective action by reprogramming the device address.
Always set this bit = 0.
I
Set by user to enable I
Clear to disable I
2
2
2
2
2
2
C stop condition detected interrupt enable bit.
C no acknowledge enable bit.
C slave SCL stretch enable bit.
C early transmit interrupt enable bit.
C general call status and ID clear bit.
C slave enable bit.
2
C slave mode.
2
C slave mode.
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2
C system. If it receives a 0x04 (write programmable part of the slave
2
C interface resets as per the I
2
C January 2000 bus specification.
2
C bus.
2
C January 2000 bus specification. This
2
C general call, Address 0x00
ADuC7060