CS1D-IC102D Omron, CS1D-IC102D Datasheet - Page 397

• Manufacturer Part Number: CS1D-IC102D
• Description: CS1D Dual IO Control Unit
• Manufacturer: Omron

Specifications of CS1D-IC102D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Instruction Execution Times and Number of Steps
9-5-4
362
FOR LOOP
BREAK LOOP
NEXT LOOP
TIMER
COUNTER
HIGH-SPEED
TIMER
ONE-MS
TIMER
ACCUMULA-
TIVE TIMER
LONG TIMER
MULTI-OUT-
PUT TIMER
REVERSIBLE
COUNTER
Instruction
Instruction
Timer and Counter Instructions
FOR
BREAK
NEXT
TIM
TIMX
CNT
CNTX
TIMH
TIMHX
TMHH
TMHHX
TTIM
TTIMX
TIML
TIMLX
MTIM
MTIMX
CNTR
CNTRX
Mnemonic
Mnemonic
Note
512
514
513
---
550
---
546
015
551
540
552
087
555
542
553
543
554
012
548
Code
Code
1. When a double-length operand is used, add 1 to the value shown in the
2. Not supported by Duplex CPU Systems.
length column in the following table.
2
1
1
3
3
3
3
3
3
3
3
3
3
4
4
4
4
3
3
Length
Length
(steps)
(steps)
0.12
0.12
0.17
0.12
0.56
0.56
0.56
0.56
0.88
0.88
0.86
0.86
16.1
10.9
8.5
16.1
10.9
8.5
7.6
6.2
7.6
6.2
20.9
5.6
20.9
5.6
16.9
16.9
CPU6@H
CPU6@H
(Duplex
(Duplex
CPU)
CPU)
Execution time ( s)
Execution time ( s)
0.12
0.12
0.17
0.12
0.56
0.56
0.56
0.56
0.88
0.88
0.86
0.86
16.1
10.9
8.5
16.1
10.9
8.5
7.6
6.2
7.6
6.2
20.9
5.6
20.9
5.6
16.9
16.9
CPU6@S
CPU6@S
(Single
(Single
CPU)
CPU)
0.21
0.12
0.17
0.12
0.88
0.88
0.88
0.88
1.14
1.14
1.12
1.12
17.0
11.4
8.7
17.0
11.4
8.7
10.0
6.5
10.0
6.5
23.3
5.8
23.3
5.8
19.0
19.0
CPU4@S
CPU4@S
(Single
(Single
CPU)
CPU)
Designating a con-
stant
---
When loop is con-
tinued
When loop is
ended
---
---
---
---
---
---
---
---
---
When resetting
When interlocking
---
When resetting
When interlocking
---
When interlocking
---
When interlocking
---
When resetting
---
When resetting
---
---
Conditions
Conditions
Section 9-5