FDW2512NZ Fairchild Semiconductor, FDW2512NZ Datasheet
FDW2512NZ
Specifications of FDW2512NZ
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FDW2512NZ Summary of contents
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... Battery disconnect circuits Pin 1 TSSOP-8 ©2008 Fairchild Semiconductor Corporation FDW2512NZ Rev. A1 General Description = 4.5V This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has = 2.5V GS been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance ...
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... C Output Capacitance OSS C Reverse Transfer Capacitance RSS R Gate Resistance G Q Total Gate Charge at 4.5V g(TOT) Q Total Gate Charge at 2.5V g(2.5) Q Gate to Source Gate Charge gs Q Gate to Drain “Miller” Charge gd FDW2512NZ Rev =25°C unless otherwise noted A Parameter 4.5V C/ 2.5V C/ Package Reel Size ...
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... Reverse Recovered Charge RR Notes C/W (steady state) when mounted inch 114 C/W (steady state) when mounted on a mininum copper pad on FR- The diode connected to the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 4 FDW2512NZ Rev 4.5V 10V 6. 4.5V ...
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... DUTY CYCLE - DESCENDING ORDER 1 0.5 0.2 0.1 0.05 0.02 0.01 0.1 0. Figure 3. Normalized Maximum Transient Thermal Impedance 400 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100 FDW2512NZ Rev 25°C unless otherwise noted 100 125 150 Figure 2. Maximum Continuous Drain Current RECTANGULAR PULSE DURATION ( PULSE WIDTH (s) Figure 4 ...
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... DRAIN TO SOURCE VOLTAGE (V) DS Figure 7. Saturation Characteristics 1.50 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 1.25 1.00 0.75 -80 - JUNCTION TEMPERATURE ( J Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature FDW2512NZ Rev. A1 (Continued 25°C unless otherwise noted A 40 100 s 30 1ms 20 10ms 1.0 30 Figure 6. Transfer Characteristics ...
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... T , JUNCTION TEMPERATURE ( J Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 4.5 3.0 1.5 Figure 13. Gate Charge Waveforms for Constant Gate Currents FDW2512NZ Rev. A1 (Continued 25°C unless otherwise noted A 1000 200 70 80 120 160 0 Figure 12. Capacitance vs Drain to Source V = 10V ...
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... Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK Figure 14. Unclamped Energy Test Circuit g(REF) Figure 16. Gate Charge Test Circuit Figure 18. Switching Time Test Circuit FDW2512NZ Rev DUT I AS 0.01 0 Figure 15. Unclamped Energy Waveforms DUT g(REF) 0 Figure 17. Gate Charge Waveforms ...
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... PSPICE Electrical Model .SUBCKT FDW2512NZ rev July 2004 8.8e- 8.8e-10 CIN 6 8 0.5e-9 DBODY 5 7 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DESD1 91 9 DESD1MODE DESD2 91 7 DESD2MOD EBREAK 22.2 EDS EGS ESG EVTHRES EVTEMP LGATE GATE 9 1 LDRAIN 2 5 1e-9 LGATE ...
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... FDW2512NZ Rev. A1 DPLCAP 10 RSLC2 - 6 ESG 8 EVTHRES + ...
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... RTHERM2 c2 c3 0.25 RTHERM3 c3 c4 1.0 RTHERM4 c4 c5 1.1 RTHERM5 c5 c6 7.5 RTHERM6 c6 c7 33.6 RTHERM7 c7 c8 33.7 RTHERM8 c8 Ambient 33.8 SABER Thermal Model SABER thermal model FDW2512NZ Minimum copper pad area template thermal_model th tl thermal_c th ctherm.ctherm1 5.7e-4 ctherm.ctherm2 5.72e-4 ctherm.ctherm3 5.8e-4 ctherm ...
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... Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production FDW2512NZ Rev. A1 FPS™ PDP-SPM™ F-PFS™ Power-SPM™ ® FRFET PowerTrench Global Power Resource SM Programmable Active Droop™ ...