FDMA520PZ Fairchild Semiconductor, FDMA520PZ Datasheet - Page 4

• Manufacturer Part Number: FDMA520PZ
• Description: MOSFET P-CH 20V 7.3A MLP2X2
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDMA520PZ

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 30 mOhm @ 7.3A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 7.3A
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 20nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 1645pF @ 10V
• Power - Max: 900mW
• Mounting Type: Surface Mount
• Package / Case: 6-MLP, 6-MicroFET™
• Transistor Polarity: P Channel
• Continuous Drain Current Id: 7.3A
• Drain Source Voltage Vds: 20V
• On Resistance Rds(on): 30mohm
• Rds(on) Test Voltage Vgs: 12V
• Threshold Voltage Vgs Typ: -1.1V
• Rohs Compliant: Yes
• Configuration: Single Quad Drain
• Resistance Drain-source Rds (on): 30 mOhms
• Forward Transconductance Gfs (max / Min): 22 S
• Drain-source Breakdown Voltage: - 20 V
• Gate-source Breakdown Voltage: +/- 12 V
• Continuous Drain Current: 7.3 A
• Power Dissipation: 2.4 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDMA520PZTR

FDMA520PZ Rev.B2
Typical Characteristics
Figure 9.
1E-4
1E-5
1E-6
1E-7
1E-8
1E-9
150
120
Figure 7.
90
60
30
10
10
0
8
6
4
2
0
Figure 11.
0
0
-4
V
I
D
GS
= -7.3A
10
T
Gate Leakage Current vs Gate to
= 0V
J
-V
-3
= 125
GS
Power Dissipation
Gate Charge Characteristics
7
3
, GATE TO SOURCE VOLTAGE(V)
Source Voltage
Single Pulse Maximum
o
10
t, PULSE WIDTH (s)
- Q
C
-2
g
, GATE CHARGE(nC)
14
10
6
-1
T
J
= 25
V
DD
10
T
V
o
DD
J
= -5V
C
0
21
9
= 25°C unless otherwise noted
= -15V
10
SINGLE PULSE
R
T
A
1
JA
=25
= 145
28
V
12
o
C
DD
10
2
o
= -10V
C/W
10
35
15
3
4
Figure 12. Transient Thermal Response Curve
3000
0.005
1000
0.01
0.01
100
0.1
30
10
0.1
60
1
2
1
0.1
0.1
10
-4
Figure 8.
r
V
SINGLE PULSE
R
T
D = 0.5
DUTY CYCLE-DESCENDING ORDER
f = 1MHz
V
DS(on)
Figure 10. Forward Bias Safe
A
GS
GS
JA
=
=4.5V
0.2
0.1
0.05
0.02
0.01
=
25
10
t, RECTANGULAR PULSE DURATION (s)
145
= 0V
LIMIT
V
-V
o
DS
-3
C
SINGLE PULSE
o
DS
to Source Voltage
C/W
, DRAIN to SOURCE VOLTAGE (V)
, DRAIN TO SOURCE VOLTAGE (V)
Operating Area
Capacitance vs Drain
10
NOTES:
DUTY FACTOR: D = t
PEAK T
-2
1
10
1
J
= P
-1
DM
10
x Z
0
P
JA
DM
1
/t
x R
2
10
10
JA
1
t
www.fairchildsemi.com
1
+ T
t
2
C
A
C
C
10
10
iss
100ms
1s
10s
rss
100us
1ms
10ms
DC
oss
2
20
60
10
3