LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet
LAN9221-ABZJ
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LAN9221-ABZJ Summary of contents
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... Reduced Power Modes — Numerous power management modes — Wake on LAN — Magic packet wakeup — Wakeup indicator event signal — Link Status Change SMSC LAN9221/LAN9221i LAN9221/LAN9221i High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Single chip Ethernet controller — ...
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... LAN9221-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +70°C TEMP RANGE) LAN9221i-ABZJ FOR 56-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO +85°C TEMP RANGE) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...
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... Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.3 Internal PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.11 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.11.1 Hardware Reset Input (nRESET 3.11.2 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.11.3 Soft Reset (SRST 3.11.4 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMSC LAN9221/LAN9221i 3 DATASHEET Revision 2.7 (03-15-10) ...
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... RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.2 TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 System Control and Status Registers 5.3.1 ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.2 IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 4 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.5.13 PHY Special Control/Status 127 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.2 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 129 SMSC LAN9221/LAN9221i 5 DATASHEET Revision 2.7 (03-15-10) ...
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... Worst Case Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.1 56-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 6 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... Figure 3.7 Ethernet Frame with Length Field and SNAP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 3.8 Ethernet Frame with VLAN Tag and SNAP Header Figure 3.9 Ethernet Frame with multiple VLAN Tags and SNAP Header . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 3.2 LAN9221/LAN9221i Host Data Path Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 3.3 FIFO Access Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 3.4 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 3 ...
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... Table 5.6 MAC CSR Register Map 106 Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 5.8 LAN9221/LAN9221i PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 6.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 6 ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet Table 7.10 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 7.11 LAN9221/LAN9221i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 8.1 56 Pin QFN Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SMSC LAN9221/LAN9221i 9 DATASHEET Revision 2.7 (03-15-10) ...
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... The LAN9221/LAN9221i supports numerous power management and wakeup features. The LAN9221/LAN9221i can be placed in a reduced power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”, “Wake on LAN” and “Link Status Change” ...
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... LAN9221/LAN9221i Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus. The diagram shown above, describes a typical system configuration of the LAN9221/LAN9221i in a typical embedded environment. The LAN9221/LAN9221i is a general purpose, platform independent, Ethernet controller. The LAN9221/LAN9221i consists of four major functional blocks ...
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... PIO interface function. On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port internal to the LAN9221/LAN9221i. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. ...
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... A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9221/LAN9221i accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with programmable polarity ...
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... SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are supported. The LAN9221/LAN9221i host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9221/LAN9221i can be interfaced to either Big-Endian or Little-Endian processors and includes mixed endian support for FIFO accesses ...
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... XTAL1/CLKIN** 55 VDDVARIO 56 **DENOTES A MULTIFUNCTION PIN NOTE: When HP Auto-MDIX is activated, the TPO+/- pins can function as TPI+/- and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 56-QFN Pin Configuration (Top View) SMSC LAN9221/LAN9221i SMSC 56-QFN (TOP VIEW) VSS 15 DATASHEET D7 ...
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... VO8/ 1 Programmable Interrupt request. Programmable polarity, source and buffer types. VOD8 VIS 1 When driven high all accesses to the LAN9221/LAN9221i are to the Data FIFOs. In this mode, the A[7:3] upper address inputs are ignored. Table 2.2 LAN Interface Signals BUFFER NUM TYPE PINS ...
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... GPO3, TX_EN, TX_EN/TX_CLK TX_CLK EEPROM Chip EECS Select EEPROM Clock, EECLK/GPO4/ GPO4 RX_DV, RX_DV/RX_CLK RX_CLK SMSC LAN9221/LAN9221i BUFFER NUM TYPE PINS VIS/VO8 1 EEPROM Data: This bi-directional pin can be connected to a serial EEPROM DIO. This is optional. General Purpose Output 3: This pin can also ...
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... Note: Note: VO8/ 1 When programmed to do so, is asserted when the LAN9221/LAN9221i detects a wake event VOD8 and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note: 18 ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9221/LAN9221i detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then driven low again ...
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... D0 D11 37 VDD18CORE VDDVARIO 38 EEDIO/GPO3 D10 39 EECS D9 40 EECLK/GPO4 D8 41 PME D7 42 nRESET EXPOSED PAD MUST BE CONNECTED TO VSS 20 DATASHEET Datasheet DESCRIPTION PIN NUM PIN NAME 43 IRQ 44 TPO- 45 TPO+ 46 VDD33A 47 TPI- 48 TPI+ 49 VDD33A 50 EXRES 51 VDD33A 52 AMDIX_EN 53 VDD18A 54 XTAL2 55 XTAL1/CLKIN 56 VDDVARIO SMSC LAN9221/LAN9221i ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet Table 2.6 External Pull-Up/Pull-Down Resistor Values I/O VOLTAGE 3.3V +/- 300mV 2.5 +/- 10% 1.8V +/- 10% SMSC LAN9221/LAN9221i PULL-UP/PULL-DOWN RESISTOR VALUE (OHMS) 10K 7.5K 4.7K 21 DATASHEET Revision 2.7 (03-15-10) ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 2.7 Buffer Types DESCRIPTION (Note 2.2) (Note 2.2) for additional information. and the individual signal descriptions in for more information. 22 DATASHEET Datasheet (Note 2.1) (Note 2.1) (Note 2.1) (Note 2.1) Section Section 2.2, Section SMSC LAN9221/LAN9221i ...
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... Interface to the internal PHY. Checksum offload engine for calculation of layer 3 transmit and receive checksum. The transmit and receive data paths are separate within the LAN9221/LAN9221i from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. A third internal bus is used to access the MAC’ ...
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... The LAN9221/LAN9221i can store up to 250 Ethernet packets utilizing FIFOs, totaling 16K bytes, with a packet granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms of allocation. This depth of buffer storage minimizes or eliminates receive overruns. 3.2 Flow Control The LAN9221/LAN9221i Ethernet MAC supports full-duplex flow control using the pause operation and control frame ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9221/LAN9221i address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in " ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9221/LAN9221i Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9221/LAN9221i packet filter function performs an imperfect address filtering against the hash table ...
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... Upon detection, the Wake-Up Frame Received bit (WUFR) in the WUCSR is set. When the host clears the WUEN bit the LAN9221/LAN9221i will resume normal receive operation. ...
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... FILTER I BYTE MASK DESCRIPTION Table 3.4 FILTER i COMMANDS Table 3.5 describes the Filter i Offset bit fields. 28 DATASHEET Datasheet Filter 1 Reserved Filter 0 Command Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter I command register. SMSC LAN9221/LAN9221i ...
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... Setting the Magic Packet Enable bit (MPEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9221/LAN9221i MAC in the “Magic Packet” detection mode. In this mode, normal data reception is disabled, and detection logic within the MAC examines receive data for a Magic Packet. ...
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... It should be noted that Magic Packet detection can be performed when LAN9221/LAN9221i is in the power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. ...
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... Figure 3.6 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16 DST SRC 1DWORD Figure 3.7 Ethernet Frame with Length Field and SNAP Header SMSC LAN9221/LAN9221i L3 Packet Calculate Checksum Figure 3.5 Type II Ethernet Frame L3 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum 31 DATASHEET ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O {OUI[15:0], PID[15:0 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum COE_CR—Checksum Offload Engine Control Register Register) and vice versa. These functions cannot be enabled 32 DATASHEET Datasheet Section 3.13.3) enables the SMSC LAN9221/LAN9221i ...
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... TX checksum preamble to include the partial checksum. The partial checksum can be replaced by the completed checksum calculation by setting the TXCSLOC pointer to point to the location of the partial checksum. SMSC LAN9221/LAN9221i COE_CR—Checksum Offload Engine Control Table 3.7). The TX checksum preamble instructs the TXCOE 3" ...
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... If a read to the same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The LAN9221/LAN9221i will reset its read counters and restart a new cycle on the next read. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 3 ...
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... Mixed Endian Support In order to allow flexibility with a range of designs, theLAN9221/LAN9221i supports mixed endian Data FIFO accesses. The LAN9221/LAN9221i provides the ability to select Data FIFO endianess separately for accesses through the Data FIFO ports (addresses 00h-3Ch) or using the FIFO_SEL input signal. ...
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... and Status FIFO s FPO R TEN [29 _SW A P Figure 3.2 LAN9221/LAN9221i Host Data Path Diagram Data path operations for the various supported endianess and word swap configurations are illustrated in Figure 3.3. Table 3.8, "Endian Ordering Logic Operation" endian logic for each type of host access. This figure and table assume an internal byte ordering of 3- 2-1-0, where ‘ ...
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... A[ A[ HOST DATA BUS SMSC LAN9221/LAN9221i WORD_SWAP != FFFF_FFFFh (FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1) MSB LSB A[ A[ WORD_SWAP = FFFF_FFFFh (FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1) ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O FIFO Access via Data Direct FIFO Access via FIFO Port (00h-3Ch) FIFO_SEL Host Data Bus Host Data Bus D[15:8] D[7:0] D[15: DATASHEET Datasheet CSR Access Host Data Bus D[7:0] D[15:8] D[7: SMSC LAN9221/LAN9221i ...
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... Datasheet 3.9 EEPROM Interface The LAN9221/LAN9221i can optionally load its MAC address from an external serial EEPROM properly configured EEPROM is detected by the LAN9221/LAN9221i at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be loaded with the contents of the EEPROM properly configured EEPROM is not detected the responsibility of the host LAN Driver to set the IEEE addresses ...
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... If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9221/LAN9221i will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. Figure 3.4, "EEPROM Access Flow Diagram" EEPROM Read or Write operation. EEPROM Write Busy Bit = 0 Figure 3.4 EEPROM Access Flow Diagram The host can disable the EEPROM interface through the GPIO_CFG register ...
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... ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) SMSC LAN9221/LAN9221i Figure 3.5 EEPROM ERASE Cycle 0 0 ...
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... Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I Figure 3.7 EEPROM EWDS Cycle Figure 3.8 EEPROM EWEN Cycle 42 DATASHEET Datasheet t CSL t CSL SMSC LAN9221/LAN9221i ...
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... E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Table 3.9, "Required EECLK each EEPROM operation. SMSC LAN9221/LAN9221i Figure 3.9 EEPROM READ Cycle Figure 3 ...
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... Refer to Section 6.11, "EEPROM Timing," on page 139 3.10 Power Management The LAN9221/LAN9221i supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.10, “Power Management States,” ...
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... LAN9221/LAN9221i to the D0 state. System Components,” on page 142 Components,” on page Note 3.11 When the LAN9221/LAN9221i power saving state, a write of any data to the BYTE_TEST register will wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit in the PMT_CTRL register is cleared. ...
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... A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN9221/LAN9221i to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9221/LAN9221i can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Note 3.17 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.18 After a power-up, nRESET or SRST, the LAN9221/LAN9221i will automatically check for the presence of an external EEPROM. After any of these resets the application must verify ...
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... PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high. After the “READY” bit is set, the LAN9221/LAN9221i can be configured via its control registers. The nRESET signal is pulled-high internally by the LAN9221/LAN9221i and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period as defined in Timing," ...
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... Start Offset” pointer will be ignored. When a packet is split into multiple buffers, each successive buffer may begin on any arbitrary byte. The LAN9221/LAN9221i can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9221/LAN9221i is operating in a system that always performs multi-word bursts ...
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... TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32- bit values that are used by the LAN9221/LAN9221i in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure ...
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... Optional offset DWORD0 3rd . . . Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Optional Pad DWORDn Last Figure 3.14 TX Buffer Format Format", shows the TX Buffer written into the LAN9221/LAN9221i DATASHEET Datasheet 0 for a detailed explanation on SMSC LAN9221/LAN9221i ...
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... Buffer Size (bytes). This field indicates the number of bytes contained in the buffer following this command. This value, along with the Buffer End Alignment field, is read and checked by the LAN9221/LAN9221i and used to determine how many extra DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9221/LAN9221i of the cumulative buffer sizes for a given packet. This cumulative value is compared against the Packet Length field in the TX command ‘ ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 3.13 TX Command 'B' Format DESCRIPTION Register, the TX checksum offload engine (TXCOE) Table 3.14, "TX DATA Start Table 3.14 TX DATA Start Offset 11 10 D[31:24] D[23:16] 54 DATASHEET Datasheet Offset", shows the 01 00 D[15:8] D[7:0] SMSC LAN9221/LAN9221i ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9221/LAN9221i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... Any DWORD-long data added as part of the End Padding is removed from each buffer before the data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the TX data FIFO Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 56 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... End Alignment” Buffer 1: 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” SMSC LAN9221/LAN9221i 57 DATASHEET Revision 2.7 (03-15-10) ...
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... TX Command 'B' 10-Byte Data Start Offset 17-Byte Payload Data 5-Byte End Padding Figure 3.15 TX Example 1 58 DATASHEET Datasheet TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes betw een buffers are not transmitted SMSC LAN9221/LAN9221i ...
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... Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9221/LAN9221i illustrates the TX command structure for this example, and also shows Data Written to the 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3 ...
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... COE_CR register. For more information, refer to Checksum Offload Engine Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O illustrates the TX command structure for this example, and also shows (TXCOE)". 60 DATASHEET Datasheet Section 3.6.2, "Transmit SMSC LAN9221/LAN9221i ...
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... Data Start Offset TX Command 'B' Packet Length = 115 TX Checksum Enable = 1 17-Byte Payload Data 5-Byte End Padding SMSC LAN9221/LAN9221i NOTE: When enabled, the TX Checksum transmitted. The FS bit in TX Command 'A', the 0 CK bit in TX Command 'B' and the TXCOE_EN bit in the COE_CR register must all be set for the TX checksum to be generated ...
Page 62
... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9221/LAN9221i can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9221/LAN9221i is operating in a system that always performs multi-DWORD bursts ...
Page 63
... The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Last Packet Figure 3.18 Host Receive Routine Using Interrupts Figure 3.19 Host Receive Routine with Polling SMSC LAN9221/LAN9221i init Idle RX Interrupt Read RX ...
Page 64
... RX status FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9221/LAN9221i receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register ...
Page 65
... RX Data FIFO. The RX checksum is enabled by setting the RXCOE_EN bit in the Control Register. For more information on the RX checksum, refer to Checksum Offload Engine SMSC LAN9221/LAN9221i Figure 3.20 assumed that the host has previously read the associated 31 Optional offset DWORD0 ...
Page 66
... Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 31 Order Optional offset DWORD0 1st . 2nd . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD RX Checksum Optional Pad DWORD0 . . Optional Pad DWORDn Last DESCRIPTION 66 DATASHEET Datasheet 0 SMSC LAN9221/LAN9221i ...
Page 67
... If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN9221/LAN9221i DESCRIPTION 67 DATASHEET Revision 2.7 (03-15-10) ...
Page 68
... Encoder 125 Mbps Serial MLT-3 Tx MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 68 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Table 4.1. Each 4-bit data-nibble SMSC LAN9221/LAN9221i ...
Page 69
... INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV 00010 V INVALID, RX_ER if during RX_DV 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER if during RX_DV SMSC LAN9221/LAN9221i Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 0110 0111 ...
Page 70
... The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 70 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID SMSC LAN9221/LAN9221i ...
Page 71
... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN9221/LAN9221i 100M PLL 25MHz 4B/5B ...
Page 72
... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 72 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 73
... Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. SMSC LAN9221/LAN9221i 73 DATASHEET Revision 2.7 (03-15-10) ...
Page 74
... Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 74 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 75
... Parallel Detection If the LAN9221/LAN9221i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. ...
Page 76
... Mbps Note 4.1 The LAN9221/LAN9221i 10/100 PHY internal CRS signal operates in two modes: Active and Low. When in Active mode, the internal CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, the internal CRS stays low and does not indicate carrier detection ...
Page 77
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9221/LAN9221i is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct cable connection vs. Cross-over cable connection. ...
Page 78
... Chapter 5 Register Description The following section describes all LAN9221/LAN9221i registers and data ports. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h 3Ch 24h 20h 1Ch 04h Base + 00h Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O ...
Page 79
... LAN9221/LAN9221i registers accordingly. 5.2 RX and TX FIFO Ports The LAN9221/LAN9221i contains four host-accessible FIFOs: RX Status, RX Data, TX Status, and TX Data FIFOs. The sizes Data FIFOs and the RX Status FIFO are configurable through the CSRs. 5.2.1 RX FIFO Ports The RX Data Path contains two Read-Only FIFOs: RX Status and RX Data ...
Page 80
... Automatic Flow Control Configuration EEPROM Command EEPROM Data Reserved for future use 80 DATASHEET Datasheet DEFAULT See Page 81. 00000000h 00000000h 00000000h - 87654321h 48000000h 00000000h 00000000h 00050000h 00000000h 00000000h 00001200h 00000000h 00000000h 0000FFFFh 0000FFFFh - 00000000h - 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h - SMSC LAN9221/LAN9221i ...
Page 81
... IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ output is disabled and permanently deasserted. This bit has no effect on any internal interrupt status bits. 7-5 Reserved SMSC LAN9221/LAN9221i 50h Size: DESCRIPTION 54h Size: ...
Page 82
... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 82 DATASHEET Datasheet TYPE DEFAULT R/W 0 NASR RO - R/W 0 NASR SMSC LAN9221/LAN9221i ...
Page 83
... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9221/LAN9221i. The LAN9221/LAN9221i will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 84
... GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 84 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN9221/LAN9221i ...
Page 85
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2-0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN9221/LAN9221i 5Ch Size: DESCRIPTION 85 DATASHEET 32 bits TYPE DEFAULT R R/W ...
Page 86
... RX Status FIFO Level interrupt (RSFL) will be generated. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 64h Size: DESCRIPTION 68h Size: DESCRIPTION 86 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN9221/LAN9221i ...
Page 87
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9221/LAN9221i will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
Page 88
... TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9221/LAN9221i Ethernet Controller. BITS 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero. ...
Page 89
... TX_CLK running), the reset will not complete and the soft reset operation will timeout and this bit will be set to a ‘1’. The host processor must correct the problem and issue another soft reset. SMSC LAN9221/LAN9221i 74h Size: for details on stopping the transmitter and receiver ...
Page 90
... After a PHY reset, or when returning from a reduced power state, the PHY must given adequate time to return to the operational state before a soft reset can be issued. The LAN9221/LAN9221i must always be read at least once after power- up, reset, or upon return from a power-saving state or write operations will not function. ...
Page 91
... SMSC LAN9221/LAN9221i Table 5.3 Valid TX/RX FIFO Allocations TX STATUS FIFO RX DATA FIFO SIZE (BYTES) 512 512 512 512 512 512 512 512 512 512 512 512 512 91 DATASHEET RX STATUS FIFO ...
Page 92
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9221/LAN9221i moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 93
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9221/LAN9221i Ethernet Controller. BITS 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO ...
Page 94
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9221/LAN9221i Note: The LAN9221/LAN9221i must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS 31:14 ...
Page 95
... This bit does not affect the PME interrupt (PME_INT). 0 Device Ready (READY). When set, this bit indicates that LAN9221/LAN9221i is ready to be accessed. This register can be read when LAN9221/LAN9221i is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9221/LAN9221i has stabilized and is fully alive ...
Page 96
... Reserved Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 96 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 0000 RO - SMSC LAN9221/LAN9221i ...
Page 97
... Timer is put into the run state. When cleared, the GP Timer is halted. On the transition of this bit the GPT_LOAD field will be preset to FFFFh. 28-16 Reserved 15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded into the GP-Timer. SMSC LAN9221/LAN9221i DESCRIPTION Table 5.4 EEPROM Enable Bit Definitions EEDIO FUNCTION EEDIO GPO3 GPO3 ...
Page 98
... This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs inside the LAN9221/LAN9221i. The LAN9221/LAN9221i always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 99
... BITS 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9221/LAN9221i 9Ch Size: DESCRIPTION A0h Size: DESCRIPTION ...
Page 100
... MAC CSR Data. Value read from or written to the MAC CSR’s. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O A4h Size: DESCRIPTION A8h Size: DESCRIPTION 100 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h 32 bits TYPE DEFAULT R/W 00000000h SMSC LAN9221/LAN9221i ...
Page 101
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9221/LAN9221i will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31:24 ...
Page 102
... BITS 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9221/LAN9221i will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9221/LAN9221i is operating in full-duplex mode. ...
Page 103
... Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. SMSC LAN9221/LAN9221i B0h Size: DESCRIPTION 103 DATASHEET ...
Page 104
... Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION [28] OPERATION 0 0 READ 0 1 EWDS 1 0 EWEN 1 1 WRITE 0 0 WRAL 0 1 ERASE 1 0 ERAL 1 1 Reload 104 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9221/LAN9221i ...
Page 105
... This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM. BITS 31-8 Reserved 7:0 EEPROM Data. Value read from or written to the EEPROM. SMSC LAN9221/LAN9221i DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 105 ...
Page 106
... Multicast Hash Table Low MII Access MII Data Flow Control VLAN1 Tag VLAN2 Tag Wake-up Frame Filter Wake-up Control and Status Checksum Offload Engine Control 106 DATASHEET Datasheet DEFAULT 00040000h 0000FFFFh FFFFFFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h SMSC LAN9221/LAN9221i ...
Page 107
... Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. 15 Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved SMSC LAN9221/LAN9221i 1 Attribute: 00040000h Size: DESCRIPTION 107 ...
Page 108
... BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9221/LAN9221i will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 109
... Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY. When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY. 1-0 Reserved SMSC LAN9221/LAN9221i DESCRIPTION BOLMT Value # Bits Used from LFSR Counter 2’b00 2’ ...
Page 110
... Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9221/LAN9221i device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed ...
Page 111
... Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9221/LAN9221i device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. ...
Page 112
... Lower 32 bits of the 64-bit Hash Table Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: 00000000h Size: for further details. DESCRIPTION 112 DATASHEET Datasheet R/W 32 bits R/W 32 bits Table 5.4.4, SMSC LAN9221/LAN9221i ...
Page 113
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9221/LAN9221i to read or write any of the MII PHY registers. ...
Page 114
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9221/LAN9221i will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 115
... VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. SMSC LAN9221/LAN9221i 9 Attribute: 00000000h ...
Page 116
... Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O B Attribute: 00000000h Size: DESCRIPTION C Attribute: 00000000h Size: DESCRIPTION 116 DATASHEET Datasheet WO 32 bits R/W 32 bits SMSC LAN9221/LAN9221i ...
Page 117
... This bit may only be changed if the RX data path is disabled. 0: The RXCOE is bypassed 1: The RXCOE is enabled Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC_CR—MAC Control simultaneously. SMSC LAN9221/LAN9221i D Attribute: 00000000h Size: DESCRIPTION Register) and vice versa. These functions cannot be enabled 117 ...
Page 118
... PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9221/LAN9221i PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 119
... Duplex Mode full duplex half duplex. Ignored if Auto Negotiation is enabled (0.12 = 1). 7 Collision Test enable COL test disable COL test 6-0 Reserved Note 5.1 The default value of this bit is determined by the auto-negotiation process. SMSC LAN9221/LAN9221i 0 Size: DESCRIPTION 119 DATASHEET 16-bits TYPE ...
Page 120
... PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 1 Size: DESCRIPTION 2 Size: DESCRIPTION 120 DATASHEET Datasheet 16-bits TYPE DEFAULT RO/ RO/LL 0 RO/ 16-bits TYPE DEFAULT RO 0x0007h SMSC LAN9221/LAN9221i ...
Page 121
... Selector Field. [00001] = IEEE 802.3 Note 5.2 When both symmetric PAUSE and asymmetric PAUSE support are advertised (value of 11), the device will only be configured to, at most, one of the two settings upon auto- negotiation completion. SMSC LAN9221/LAN9221i 3 Size: DESCRIPTION 4 Size: DESCRIPTION Note 5 ...
Page 122
... Selector Field. [00001] = IEEE 802.3 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 5 Size: DESCRIPTION 122 DATASHEET Datasheet 16-bits TYPE DEFAULT 00001 SMSC LAN9221/LAN9221i ...
Page 123
... Reset to “1” by hardware reset, unaffected by SW reset. 0 Reserved. Write as “0”. Ignore on read. Note 5.3 The default value of this bit will vary dependant on the current link state of the line. SMSC LAN9221/LAN9221i 6 Size: DESCRIPTION 17 Size: DESCRIPTION ...
Page 124
... CRS is active during Transmit & Receive. 101 Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9221/LAN9221i in this mode. 111 All capable. Auto-negotiation enabled. Note 5.4 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto- negotiated speed and duplex ...
Page 125
... Receive PLL 10M is locked on the reference clock. In this mode 10M data packets cannot be received. 9-5 Reserved: Write as 0. Ignore on read. 4 XPOL: Polarity state of the 10Base- Normal polarity 1 - Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. SMSC LAN9221/LAN9221i 27 Size: DESCRIPTION 125 DATASHEET 16-bits MODE DEFAULT RW ...
Page 126
... Mask Bits interrupt source is enabled 0 = interrupt source is masked Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 29 Size: DESCRIPTION 30 Size: DESCRIPTION 126 DATASHEET Datasheet 16-bits TYPE DEFAULT RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH See Note 5.5 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 16-bits TYPE DEFAULT SMSC LAN9221/LAN9221i ...
Page 127
... Speed Indication. HCDSPEED value: [001]=10Mbps half-duplex [101]=10Mbps full-duplex [010]=100Base-TX half-duplex [110]=100Base-TX full-duplex 1-0 Reserved. Write as 0; ignore on Read Note 5.6 The default value of this bit is determined by the auto-negotiation process. SMSC LAN9221/LAN9221i 31 Size: DESCRIPTION 127 DATASHEET 16-bits TYPE DEFAULT ...
Page 128
... Output timing specifications assume an equivalent test load as illustrated in OUTPUT 6.2 Host Interface Timing The LAN9221/LAN9221i supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Reads (nCS or nRD controlled) ...
Page 129
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9221/LAN9221i before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 130
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9221/LAN9221i, and the subsequent indication of the expected change in the control register values. ...
Page 131
... Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN9221/LAN9221i Figure 6.2 PIO Read Cycle Timing Table 6.3 PIO Read Timing time is 9ns ...
Page 132
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Figure 6.3 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing time is 9ns. doff 132 DATASHEET Datasheet MIN TYP MAX UNITS Note 6 time is 7ns. When VDDVARIO is doff SMSC LAN9221/LAN9221i ...
Page 133
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9221/LAN9221i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9221/LAN9221i ...
Page 134
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9221/LAN9221i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line ...
Page 135
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet 6.7 PIO Writes PIO writes are used for all LAN9221/LAN9221i write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. A[7:1] ...
Page 136
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9221/LAN9221i will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9221/LAN9221i ...
Page 137
... Note: Power must be applied and removed to all 3.3V power supply pins simultaneously (including the Ethernet magnetics). Note: Power must be applied and removed to all VDDVARIO power supply pins simultaneously. SMSC LAN9221/LAN9221i t pon Figure 6.8 Power Sequence Timing Table 6.9 Power Sequence Timing ...
Page 138
... Output Drive after nRESET rising Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O T6.1 T6.2 T6.3 T6.4 Figure 6.9 Reset Timing Table 6.10 Reset Timing MIN TYP MAX 30 200 10 16 138 DATASHEET Datasheet UNITS NOTES SMSC LAN9221/LAN9221i ...
Page 139
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet 6.11 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9221/LAN9221i: SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK ...
Page 140
... Supply Voltage (VDD33REG, VDD33A +3.3V+/-300mV Ambient Operating Temperature in Still Air (T Note: Do not drive input signals without power supplied to the device. **Proper operation of the LAN9221/LAN9221i is guaranteed only within the ranges specified in this section. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O ...
Page 141
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet 7.3 Power Consumption (Device Only) This section provides typical power consumption values for the LAN9221/LAN9221i in various modes of operation. These measurements were taken under the following conditions: Temperature: ................................................................................................................................... +25°C Device VDD (VDDVARIO, VDD33REG, VDD33A): ....................................................................... +3.30V Note: Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink requirements ...
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... Power Consumption (Device and System Components) This section provides typical power consumption values for a complete Ethernet interface based on the LAN9221/LAN9221i, including the power dissipated by the magnetics and other passive components. Note: The power measurements list below were taken under the following conditions: Temperature: ................................................................................................................................... +25° ...
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... Variable Voltage Supply Current +3.3V Regulator Supply Current +3.3V Analog Supply Current Note: Above values do not include the supply current for the magnetics. Based on the recommended implementation, the maximum supply current needed for the magnetics is 108mA. SMSC LAN9221/LAN9221i Table 7. for commercial version, -40 ...
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... DC Electrical Specifications This section details the DC electrical specifications of the LAN9221/LAN9221i I/O buffers. The electrical specifications in this section are valid over the indicated voltage range and the temperature range specified in Section 7.2, "Operating Note: When operating at reduced VDDVARIO voltage levels (less than 3.0V), do not rely on internal pull-up and pull-down resistors to determine signal state ...
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... V OL VO8 Type Buffer Low Output Level V OL High Output Level V OH ICLK Input Buffer Low Input Level V ILCK High Input Level V IHCK SMSC LAN9221/LAN9221i MIN TYP MAX -0.3 0.78 0.94 1.13 1.32 1.51 304 384 -10 IN VDDVARIO - 0.4 VDDVARIO - 0.4 -0 ...
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... MAX to calculate per-pin leakage. For example pins IN 146 DATASHEET Datasheet UNITS NOTES Schmitt Trigger V Schmitt Trigger 525 mV +10 uA Note 7.8 120 uA Note 7.8, Note 7.9 2 4mA -4mA OH 0 4mA OL 0 3mA OL 0 3mA -3mA OH 0.5 V 3.6 V Chapter 2, Pin (5.5V or 5.25V, dependant on IN SMSC LAN9221/LAN9221i ...
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... Note 7.11 Offset from16 nS pulse width at 50% of pulse peak Note 7.12 Measured differentially. Table 7.10 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.13 Min/Max voltages guaranteed as measured with 100Ω resistive load. SMSC LAN9221/LAN9221i SYMBOL MIN TYP MAX V 950 - 1050 ...
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... Clock Circuit The LAN9221/LAN9221i can accept either a 25MHz crystal (preferred MHz single-ended clock oscillator (±50 PPM) input. The LAN9221/LAN9221i shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum ...
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... Position tolerance of each terminal and exposed pad is ± 0. maximum material condition. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3. The pin 1 identifier may vary, but is always located within the zone indicated. SMSC LAN9221/LAN9221i MAX REMARKS 1.00 Overall Package Height 0 ...
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... Figure 8.2 56 Pin QFN Recommended PCB Land Pattern Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 150 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... Power Signals,” on page 18 Rev. 2.2 Auto-negotiation Advertisement on page 121 (06-10-08) SMSC LAN9221/LAN9221i Table 9.1 Customer Revision History Added pin 1 designator to pin diagram Added note: “Do not drive input signals without power supplied to the device.” Added power sequence timing section ...
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... Removed the system memory block and arrow above the microprocessor/ microcontroller Pin assignment information re-organized into separate table. Note added to EECLK pin description to indicate proper usage. 152 DATASHEET Datasheet CORRECTION WUCSR—Wake- Register, a broadcast wake- Register.” SMSC LAN9221/LAN9221i ...