LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 135
LAN9221-ABZJ
Manufacturer Part Number
LAN9221-ABZJ
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of LAN9221-ABZJ
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (min)
1.62V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
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High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
6.7
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
PIO writes are used for all LAN9221/LAN9221i write cycles. PIO writes can be performed using Chip
Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between
cycles for the period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 6.6 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
135
MIN
45
32
13
0
7
0
0
TYP
MAX
Revision 2.7 (03-15-10)
UNITS
ns
ns
ns
ns
ns
ns
ns
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