LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 46

• Manufacturer Part Number: LAN9221-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
Note 3.16 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9221/LAN9221i to the D0 state and will reset the PM_MODE field to the D0 state. As noted above,
the host is required to check the READY bit and verify that it is set before attempting any other reads
or writes of the device. Before the LAN9221/LAN9221i is fully awake from this state the EDPWRDOWN
bit in register 17 of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the
EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the
LAN9221/LAN9221i is ready to resume normal operation. At this time the WUPS field can be cleared.
setting of PME_EN.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.10 Power Management States
D0
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
DATASHEET
RX Power Mgmt. Block
46
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
SMSC LAN9221/LAN9221i
OFF
OFF
OFF
D2
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