LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 35

• Manufacturer Part Number: LAN9221-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
3.7.3
3.7.4
Mixed Endian Support
In order to allow flexibility with a range of designs, theLAN9221/LAN9221i supports mixed endian Data
FIFO accesses. The LAN9221/LAN9221i provides the ability to select Data FIFO endianess separately
for accesses through the Data FIFO ports (addresses 00h-3Ch) or using the FIFO_SEL input signal.
This is accomplished via the FPORTEND and FSELEND bits of the
Configuration
The FPORTEND bit determines the endianess of RX and TX Data FIFO host accesses made through
the Data FIFO port addresses (00h-3Ch). When FPORTEND is cleared, Data FIFO port accesses
utilize little endian byte ordering. When FPORTEND is set, Data FIFO port accesses utilize big endian
byte ordering.
The FSELEND bit determines the endianess of RX and TX Data FIFO host accesses when using the
FIFO_SEL signal. When FSELEND is cleared, FIFO_SEL accesses utilize little endian byte ordering.
When FSELEND is set, FIFO_SEL accesses utilize big endian byte ordering.
In addition to mixed endian support, the LAN9221/LAN9221i provides a word swap function, as
described in
above determines how the Data/Status FIFO’s and CSR host access byte ordering is applied.
describes the various operation modes of the endianess and word swap ordering logic.
illustrates the FIFO access byte ordering under various endianess and word swap settings. Refer to
Section 3.7.4
Note: CSR and status FIFO accesses are not affected by the FPORTEND and FSELEND endianess
Word Swap Function
In addition to mixed endian functionality, the LAN9221/LAN9221i supports a Word Swap Function. This
feature is controlled by the Word Swap Register, which is described in
"WORD_SWAP—Word Swap Control," on page
are written to or read from the Control and Status Registers and the Transmit and Receive Data/Status
FIFOs.
Both the word swap function and the mixed endian control bits contain the ability to change the byte
ordering of host data path accesses.
endianess select logic is applied within the LAN9221/LAN9221i. Logically, the endian control logic is
applied after the word swap logic for write operations, and before the word swap logic for read
operations.
select bits.
Section
for additional details.
Register, respectively.
3.7.4. The word swap function combined with the endianess select bits described
DATASHEET
Figure 3.2
35
98. This register affects how words on the data bus
illustrates the order in which the word swap and
HW_CFG—Hardware
Revision 2.7 (03-15-10)
Section 5.3.17,
Figure 3.3
Table 3.8