LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 44

• Manufacturer Part Number: LAN9221-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
3.9.2.2
3.9.2.3
3.9.2.4
3.10
3.10.1
3.10.2
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to
"E2P_DATA – EEPROM Data Register," on page 105
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to
The LAN9221/LAN9221i supports power-down modes to allow applications to minimize power
consumption. The following sections describe these modes.
System Description
Power is reduced to various modules by disabling the clocks as outlined in Table 3.10, “Power
Management States,” on page 46. All configuration data is saved when in either of the two low power
states. Register contents are not affected unless specifically indicated in the register description.
Functional Description
There is one normal operating power state, D0 and there are two power saving states: D1, and D2.
Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for
read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be
cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the
exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when
in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed.
Power Management
OPERATION
ERASE
WRITE
EWDS
EWEN
WRAL
READ
ERAL
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 103
Section 6.11, "EEPROM Timing," on page 139
Table 3.9 Required EECLK Cycles
DATASHEET
44
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
REQUIRED EECLK CYCLES
for detailed EEPROM timing specifications.
for a detailed description of these registers.
10
10
10
10
18
18
18
SMSC LAN9221/LAN9221i
and
Section 5.3.24,
Datasheet