LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 14

• Manufacturer Part Number: LAN9221-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
1.11
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9221/LAN9221i Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9221/LAN9221i host bus interface supports 16-bit bus transfers. Internally, all data paths are
32-bits wide. The LAN9221/LAN9221i can be interfaced to either Big-Endian or Little-Endian
processors and includes mixed endian support for FIFO accesses.
14
Revision 2.7 (03-15-10)
SMSC LAN9221/LAN9221i
DATASHEET