LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 108

• Manufacturer Part Number: LAN9221-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
BITS
13
12
10
11
9
8
Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9221/LAN9221i will implement a
perfect address filter on incoming frames according the address specified in the MAC address register.
When set (1), the address check Function does imperfect address filtering of multicast incoming
frames according to the hash table specified in the multicast hash table register.
If the Hash Only Filtering mode (HO) bit is set (1), then the physical (IA) are imperfect filtered too. If
the Hash Only Filtering mode (HO) bit is reset (0), then the IA addresses are perfect address filtered
according to the MAC Address register
Late Collision Control (LCOLL). When set, enables retransmission of the collided frame even after
the collision period (late collision). When reset, the MAC disables frame transmission on a late
collision. In any case, the Late Collision status is appropriately updated in the Transmit Packet status.
Disable Broadcast Frames (BCAST). When set, disables the reception of broadcast frames. When
reset, forwards all broadcast frames to the application.
Note:
Disable Retry (DISRTY). When set, the MAC attempts only one transmission. When a collision is
seen on the bus, the MAC ignores the current frame and goes to the next frame and a retry error is
reported in the Transmit status. When reset, the MAC attempts 16 transmissions before signaling a
retry error.
Reserved
Automatic Pad Stripping (PADSTR). When set, the MAC strips the pad field on all incoming frames,
if the length field is less than 46 bytes. The FCS field is also stripped, since it is computed at the
transmitting station based on the data and pad field characters, and is invalid for a received frame
that has had the pad characters stripped. Receive frames with a 46-byte or greater length field are
passed to the Application unmodified (FCS is not stripped). When reset, the MAC passes all incoming
frames to the host unmodified.
Note:
When wake-up frame detection is enabled via the WUEN bit of the
Control and Status
state of this bit.
When PADSTR is enabled, the RX Checksum Offload Engine must be disabled (bit 0
(RXCOE_EN) of the
These functions cannot be enabled simultaneously.
Register, a broadcast wake-up frame will wake-up the device despite the
COE_CR—Checksum Offload Engine Control
DATASHEET
108
DESCRIPTION
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Register) and vice versa.
WUCSR—Wake-up
SMSC LAN9221/LAN9221i
Datasheet