LAN9221-ABZJ Standard Microsystems (SMSC), LAN9221-ABZJ Datasheet - Page 49

• Manufacturer Part Number: LAN9221-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9221-ABZJ

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.62V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately,
SMSC LAN9221/LAN9221i
3.11.1
3.11.2
3.11.3
3.11.4
3.11.4.1
3.11.4.2
3.12
Hardware Reset Input (nRESET)
A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the
PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware
reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high.
After the “READY” bit is set, the LAN9221/LAN9221i can be configured via its control registers. The
nRESET signal is pulled-high internally by the LAN9221/LAN9221i and can be left unconnected if
unused. If used, nRESET must be driven low for a minimum period as defined in
Timing," on page
reset (SRST).
Resume Reset Timing
After issuing a write to the BYTE_TEST register to wake the LAN9221/LAN9221i from a power-down
state, the READY bit in PMT_CTRL will assert (set High) within 2ms.
Soft Reset (SRST)
Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will
return to ‘0’ after approximately 2 μs, at which time the Soft Reset is complete. Soft reset does not
clear control register bits marked as NASR. Following power-on, a soft reset must not be performed
until the READY bit in the PMT_CTRL register has been set.
PHY Reset Timing
The following sections specify the operation and time required for the internal PHY to become
operational after various resets or when returning from the reduced power state.
PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This
self-clearing bit will return to ‘0’ after approximately 100 μs, at which time the PHY reset is complete.
PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register.
This self-clearing bit will return to ‘0’ at which time the PHY reset is complete.
Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may
be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command
TX Data Path Operation
reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
(within 2μs). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
138. If nRESET is unused, the device must be reset following power-up via a soft
DATASHEET
49
Section 6.10, "Reset
Revision 2.7 (03-15-10)