RD38F1020C0ZBL0 Intel, RD38F1020C0ZBL0 Datasheet

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RD38F1020C0ZBL0

Manufacturer Part Number
RD38F1020C0ZBL0
Description
Manufacturer
Intel
Datasheet

Specifications of RD38F1020C0ZBL0

Operating Supply Voltage (max)
3.3V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
RD38F1020C0ZBL0
Manufacturer:
ETRONTECH
Quantity:
378
Intel
Memory (C3)
SCSP Family
Product Features
The Intel
device delivers a feature-rich solution for low-power applications. The C3 SCSP memory device
incorporates flash memory and static RAM in one package with low voltage capability to
achieve the smallest system memory solution form-factor together with high-speed, low-power
operations. The C3 SCSP memory device offers a protection register and flexible block locking
to enable next generation security capability. Combined with the Intel
(Intel
data storage solution.
Flash Memory Plus SRAM
SCSP Technology
Advanced SRAM Technology
Intel
Software
— Reduces Memory Board Space
— Smallest Memory Subsystem Footprint
— Area : 8 x 10 mm for 16 Mbit (0.13 µm)
— Area : 8 x 12 mm for 32 Mbit (0.13 µm)
— Height : 1.20 mm for 16 Mbit (0.13 µm)
— Height : 1.40 mm for 32 Mbit (0.13 µm)
— This Family also includes 0.25 µm, 0.18
— 70 ns Access Time
— Low Power Operation
— Low Voltage Data Retention Mode
— Real-Time Data Storage and Code
— Full Flash File Manager Capability
®
Required, Simplifying PCB Design
Complexity
Flash + 2 Mbit or 4 Mbit SRAM
Flash + 4 Mbit or 8 Mbit SRAM
Flash + 2 Mbit or 4 Mbit SRAM, and 32
Mbit (0.13um) Flash + 8 Mbit SRAM
Flash + 4 Mbit SRAM
µm, and 0.13 µm technologies
Execution in the Same Memory Device
FDI) software, the C3 SCSP memory device provides a cost-effective, flexible, code plus
®
®
Flash Data Integrator (FDI)
®
Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP)
Advanced+ Boot Block Flash
Advanced+ Boot Block Flash Memory
Blocking Architecture
Low Power Operation
Flash Technologies
—70 ns Access Time
—Instant, Individual Block Locking
—128 bit Protection Register
—12 V Production Programming
—Fast Program and Erase Suspend
—Extended Temperature –25 °C to +85 °C
—Block Sizes for Code + Data Storage
—4-Kword Parameter Blocks
—64-Kbyte Main Blocks
—100,000 Erase Cycles per Block
—Asynchronous Read Current: 9 mA
—Standby Current: 7 µA (Flash)
—Automatic Power Saving Mode
—0.25 µm ETOX™ VI, 0.18 µm ETOX™
(Flash)
VII and 0.13 µm ETOX™ VIII Flash
Technologies
Order Number: 252636, Revision: 004
®
Flash Data Integrator
Datasheet
26 Aug 2005

Related parts for RD38F1020C0ZBL0

RD38F1020C0ZBL0 Summary of contents

Page 1

... RAM in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. The C3 SCSP memory device offers a protection register and flexible block locking to enable next generation security capability. Combined with the Intel ® (Intel FDI) software, the C3 SCSP memory device provides a cost-effective, flexible, code plus data storage solution ...

Page 2

... Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. ...

Page 3

... Improved 12 Volt Production Programming ...........................................................25 4.2.2 F-VPP £ VPPLK for Complete Protection .............................................................. 25 5.0 Electrical Specifications ............................................................................................................. 26 5.1 Absolute Maximum Ratings ................................................................................................ 26 5.2 Operating Conditions .......................................................................................................... 27 5.3 Capacitance ........................................................................................................................ 27 ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Order Number: 252636, Revision: 004 C3 SCSP Flash Memory 26 Aug 2005 3 ...

Page 4

... B.3 Block Lock Status Register................................................................................................. 54 B.4 CFI Query Identification String............................................................................................ 54 B.5 System Interface Information.............................................................................................. 55 B.6 Device Geometry Definition ................................................................................................ 56 B.7 Intel-Specific Extended Query Table .................................................................................. 57 C Word-Wide Memory Map Diagrams .............................................................................................. 59 D Device ID Table ............................................................................................................................. 66 E Protection Register Addressing ..................................................................................................... 67 F Mechanical and Shipping Media Details........................................................................................ 68 F ...

Page 5

... Minor text edits. 03/05 -003 Updated Ordering Information figures and table in Appendix H. 26 Aug 2005 -004 Updated Ordering Information to add PF28F1602C3TD70. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Description Order Number: 252636, Revision: 004 C3 SCSP Flash Memory 26 Aug 2005 5 ...

Page 6

... C3 SCSP Flash Memory 1.0 Introduction This document contains the specifications for the Intel (C3) Stacked Chip Scale Package (SCSP) device. C3 SCSP memory solutions are offered in the following combinations: • 32-Mbit flash + 8-Mbit SRAM • 32-Mbit flash + 4-Mbit SRAM • 16-Mbit flash + 4-Mbit SRAM • ...

Page 7

... Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Section 5.7, “Flash Erase and Program Timings(1)” on page 34 Order Number: 252636, Revision: 004 ...

Page 8

... Ball location A10 16/2 devices only maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6 land pad directly to the land pad for the G4 (A17) ball. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family ...

Page 9

... SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ S-LB# INPUT S-LB# is active low. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Figure 1 “66-Ball SCSP Package Ballout” on page Name and Function Order Number: 252636, Revision: 004 8. –DQ ) ...

Page 10

... SRAM GROUND: For all internal circuitry. All ground inputs must be connected. NC NOT CONNECTED: Internally disconnected within the device. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 10 Name and Function ≤ protect all contents against Program and Erase commands. ...

Page 11

... S-CS1# • S-CS2 • S-OE# • S-WE# Table 2 on page 9 and ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Flash 28F160C3 or 28F320C3 SRAM 2 8-Mbit Table 3 on page 12 summarize these bus operations . Order Number: 252636, Revision: 004 F-VCCQ F-WE# ...

Page 12

... F-OE# must be asserted to obtain data from the flash memory device. The SRAM provides only one read mode. S-CS1#, S-CS2, and S-OE# must be asserted to obtain data from the SRAM device. See Table 3. Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations Flash Signals Modes Read ...

Page 13

... F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 on page 33 ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family are deasserted, the SCSP enters a standby mode, which 2 is required until outputs are valid. A delay (t ...

Page 14

... In this mode, read cycles from addresses shown in page 15 retrieve the specified information return to read array mode, write the Read Array command (FFh). ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 14 19. (reset the flash memory device defaults to read array ...

Page 15

... See Section 3.8 Intel reserves other locations within the configuration address space for future use. 3.3 Read Status Register (70h) The status register indicates the status of device operations, and the success/failure of that operation. ...

Page 16

... Programming the memory changes the value of specific bits within an address to 0. Note: If you attempt to program a 1 value, the memory cell contents do not change and no error occurs. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 16 Appendix B, “CFI Query Structure” Order Number: 252636, Revision: 004 ...

Page 17

... Read Status Register • Read Configuration • CFI Query • Program Resume. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family was not within acceptable limits, and the WSM did not execute PP Order Number: 252636, Revision: 004 26 Aug 2005 17 ...

Page 18

... When a program operation is nested within an Erase Suspend operation and the Program Suspend command is issued, the device will suspend the program ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 18 Flowcharts”). level used for program while in program suspend mode. ...

Page 19

... Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query information, respectively. 3. Either 40h or 10h command is valid, but the Intel standard is 40h. 4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle). ...

Page 20

... X = value of WP bit DQ the Block Lock status register, and Z = bit DQ Locking State Transitions” on page 23 ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 20 Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits ...

Page 21

... Lock-Down state [011] regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 23, and a flowchart for locking operations is shown in Order Number: 252636, Revision: 004 Figure 19 on ...

Page 22

... When erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an erase suspend. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 22 Address Data XX002 ...

Page 23

... The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming. ...

Page 24

... Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program FFFDh to the PR-LOCK location ...

Page 25

... When F-V any program or erase operation will result in a error, prompting the corresponding status register bit (SR. set. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family , F-V and S-V together. Conversely, F-V ...

Page 26

... These are stress ratings only. Do not operate the flash memory device beyond the Operating Conditions in affect device reliability. NOTICE: This datasheet contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a . design Table 9. ...

Page 27

... MHz CASE Table 11. Capacitance Sym Parameter C Input Capacitance IN C Output Capacitance OUT Note: Sampled, not 100% tested. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Parameter Notes /F-V /S-V Supply CCQ must share the same supply. F-V /S-V CC 11.4 V– ...

Page 28

... Operating Power Supply Current I (cycle time = 1 µs) CC Operating Power Supply Current I CC2 (min cycle time Read Current CCR CC ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 28 2.7 V – 3.3 V Device Note Typ Flash/ 1 SRAM Flash/ 1 0.2 SRAM 0.25µm ...

Page 29

... If device is read while in erase suspend, current draw is sum of CCES CCWS I and the device is read while in program suspend, current draw is the sum of I CCES CCR ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 2.7 V – 3.3 V Device Note Typ 18 Flash 1,3 8 ...

Page 30

... Note: AC test inputs are driven at V timing ends when CCQ Figure 5. Test Configuration Note: C includes jig capacitance. L ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 30 2.7 V – 3.3 V Device Note Min Flash/ –0.2 SRAM Flash/ 2.3 SRAM Flash/ – ...

Page 31

... C3 SCSP Flash Memory Flash Test Configuration Component Values Table Test Configuration 2.7 V–3.3 V Standard Test ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family C (pF Order Number: 252636, Revision: 004 26 Aug 2005 31 ...

Page 32

... See Figure 6 “AC Waveform: Flash Read Operations” on page 4. See Figure 4, “Input/Output Reference Waveform” on page 28 for timing measurements and maximum allowable input slew rate. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 32 Density 16-Mbit Product -70 -90 Voltage ...

Page 33

... WHDX EHDX Address Hold Time from F-WE# (F-CE#) High WHAX EHAX F-WE# (F-CE#) Pulse Width High WHWL EHEL ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Device and Data Address Selection Valid Address Stable Valid Output R2 R5 Parameter Order Number: 252636, Revision: 004 ...

Page 34

... EHRH1 Erase Suspend Latency WHRH2 EHRH2 Notes: 1. Typical values measured at T CASE 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 34 Parameter = WLWH ELEH = WPH WHWL EHEL for valid A F-V 1.65 V– ...

Page 35

... Write Program or Erase Setup Command. 4. Write Valid Address and Data (for Program) or Erase Confirm Command. 5. Automated Program or Erase Delay. 6. Read Status Register Data (SRD): reflects completed program/erase operation. 7. Write Read Array Command. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family ...

Page 36

... PLPH 3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. Sampled, but not 100% tested. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family RP# ( ...

Page 37

... Sampled, but not 100% tested. 4. Timings conditions and are not referenced to output voltage levels. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family (1) Parameter Read Cycle Time Address to Output Delay S-CS1#, S-CS2 to Output Delay S-OE# to Output Delay S-UB#, LB# to Output Delay ...

Page 38

... Data to Write Time Overlap Address Setup to S-WE# (S-CS AW S-CE# (S-WE#) Setup to S-WE# (S- High W7 t Data Hold Time from S-WE# (S-CS DH ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 38 Device Data Valid Address Selection Address Stable High Z Valid Output R11 R5 ...

Page 39

... IH WE# ( DATA (D/ UB#, LB ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family (1,2) Parameter #) Going High low S-CS # and low S-WE#. A write begins when S- measured from the beginning of write to the end of write going low to end of write. 1 Device Address Selection Address Stable ...

Page 40

... RDR Notes: 1. Typical values at nominal S-V CC S-CS1# ≥ V 0.2 V, S-CS2 ≥ – Figure 11. SRAM Data Retention Waveform CS CS ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 40 (1) —Extended Temperature Note Min Typ Max 1.5 – 3.3 – – – ...

Page 41

... Since the flash in SCSP shares the same features as the C3 features, conversions from the C3 are described in AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory, order number 292216. Please contact your local Intel representation for detailed information about specific Flash + SRAM system migrations. 7.0 ...

Page 42

... If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting F-RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. ...

Page 43

... It is highly recommended that systems use a 0.1 grid ballout locations (see capacitors are necessary to avoid undesired conditions created by excess noise. Smaller capacitors can be used to decouple higher frequencies. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family System Supply System Supply V CC ...

Page 44

... CC SS S-V CCQ XX Substrate connection to package ball S-X SRAM die bond pad connection Flash die bond pad connection F-X Table 2 “Intel® Advanced+ Boot Block SCSP Ball Descriptions” on page 9 Order Number: 252636, Revision: 004 A9 F-V SSQ D9 F-V D10 CC F-V A10 ...

Page 45

... The Intel SCSP will save significant space on your PCB by combining two chips into one BGA style package. Intel SCSP has a 0.8 mm pitch that can be routed on your Printed Circuit Board with conventional design rules. Trace widths of 0.127 mm (0.005 inches) are typical. Unused balls in the center of the package are not populated to further increase the routing options ...

Page 46

... Attempted Program to SR.1 = Locked Block - Aborted 0 Program Successful ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 46 Bus Operation Write Write Read Standby Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations ...

Page 47

... SR Write FFH Read Array Data No Done Reading Yes Write D0H Program Resumed 0645_13 ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Bus Operation Write Write Read Standby Standby Write Program Completed Read Write Write FFH Read Array Data ...

Page 48

... Block Erase Error 0 1 Attempted Erase of SR.1 = Locked Block - Aborted 0 Block Erase Successful 0645_14 ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 48 Bus Operation Write Write Read Suspend Erase Loop Standby Yes Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures ...

Page 49

... SR Write FFH Read Array Data No Done Reading Yes Write D0H Erase Resumed 0645_15 ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Bus Operation Write Write Read Standby Standby Write Erase Completed Read Write Write FFH Read Array Data ...

Page 50

... Write 90H (Read Configuration) Read Block Lock Status Locking Change Confirmed? Write FFh (Read Array) Locking Change Complete 0645_16 ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 50 Bus Command Command Operation Write Write Config. Setup Lock, Unlock, Write or Lockdown ...

Page 51

... Attempted Program to SR.1, SR.4 = Locked Register - Program Successful 0645_17 ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Bus Operation Write Write Read Standby Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error ...

Page 52

... Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 21. Summary of Query Structure Output as a Function of Device and Mode Device Address ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 52 Device Order Number: 252636, Revision: 004 ) only. The numerical ...

Page 53

... BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family ...

Page 54

... Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 54 Description Description Query-unique ASCII string “QRY“ Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address ...

Page 55

... Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Description µ ...

Page 56

... Erase Block Region 2 Information bits 0– y+1 = number of identical-size erase blocks bits 16– region erase block(s) size are z x 256 bytes ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 56 Description n in number of bytes 28:00,29:00 28:01,29:00 28:02,29:00 Order Number: 252636, Revision: 004 ...

Page 57

... B.7 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 28. Primary-Vendor Specific Extended Query (Sheet (1) Offset Length P = 35h (Optional Flash Features and Commands) ...

Page 58

... Reserved for future use Note: 1. The variable pointer which is defined at CFI offset 15h. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 58 Description Description n = factory pre- programmed bytes n = user programmable bytes ...

Page 59

... D8000-DFFFF 1DFFFF 1D0000- 32 D0000-D7FFF 1D7FFF 1C8000- 32 C8000-CFFFF 1CFFFF 1C0000- 32 C0000-C7FFF 1C7FFF 1B8000- 32 B8000-BFFFF 1BFFFF 1B0000- 32 B0000-B7FFF 1B7FFF ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Size 64-Mbit 16-Mbit (KW) 3FF000-3FFFFF 32 3FE000- 32 3FEFFF 3FD000- 32 3FDFFF 3FC000- 32 3FCFFF 3FB000- 32 3FBFFF 3FA000-3FAFFF 32 3F9000-3F9FFF 32 ...

Page 60

... Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 60 Size 64-Mbit 16-Mbit (KW) 3A8000- 32 3AFFFF 3A0000-3A7FFF 32 398000-39FFFF 32 390000-397FFF 32 388000-38FFFF 32 380000-387FFF 32 378000-37FFFF 32 370000-377FFF 32 368000-36FFFF ...

Page 61

... This column continues on next page ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Size 64-Mbit 16-Mbit (KW) 310000-317FFF 32 308000-30FFFF 32 300000-307FFF 32 2F8000-2FFFFF 32 2F0000-2F7FFF 32 2E8000- 32 2EFFFF 2E0000-2E7FFF 32 2D8000- 32 2DFFFF ...

Page 62

... Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 62 Size 64-Mbit 16-Mbit (KW) 2A0000-2A7FFF 32 298000-29FFFF 32 290000-297FFF 32 288000-28FFFF 32 280000-287FFF 32 278000-27FFFF 32 270000-277FFF 32 268000-26FFFF 32 260000-267FFF 32 258000-25FFFF 32 ...

Page 63

... Word-Wide Memory Addressing Top Boot Size 16-Mbit 32-Mbit (KW) 008000- 32 00FFFF 000000- 32 007FFF ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Size 64-Mbit 16-Mbit (KW) 208000-21FFFF 32 200000-207FFF 32 1F8000-1FFFFF 32 1F0000-1F7FFF 32 1E8000- 32 1EFFFF 1E0000-1E7FFF 32 1D8000- 32 1DFFFF 1D0000- 32 1D7FFF 1C8000- 32 1CFFFF 1C0000- 32 1C7FFF ...

Page 64

... Mbit Memory Addressing (Sheet 16-Mbit, 32-Mbit 64-Mbit Word-Wide Memory Addressing Top Boot Size 16-Mbit 32-Mbit (KW This column continues on next page ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 64 Size 64-Mbit 16-Mbit (KW) 170000-177FFF 32 168000-16FFFF 32 160000-167FFF 32 158000-15FFFF 32 150000-157FFF 32 148000-14FFFF 32 140000-147FFF 32 138000-13FFFF 32 130000-137FFF 32 F8000-FFFFF ...

Page 65

... Word-Wide Memory Addressing Top Boot Size 16-Mbit 32-Mbit (KW ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Size 64-Mbit 16-Mbit (KW) 0F0000-0F7FFF 32 B8000-BFFFF 0E8000- 32 B0000-B7FFF 0EFFFF 0E0000-0E7FFF 32 A8000-AFFFF 0D8000- 32 A0000-A7FFF 0DFFFF 0D0000- 32 98000-9FFFF 0D7FFF 0C8000- 32 90000-97FFF 0CFFFF 0C0000- 32 88000-8FFFF 0C7FFF ...

Page 66

... Item Manufacturer Code Device Code 16-Mbit x 16-T 16-Mbit x 16-B 32-Mbit x 16-T 32-Mbit x 16-B Note: Other locations within the configuration address space are reserved by Intel for future use. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 66 Size 64-Mbit 16-Mbit ...

Page 67

... User 1 5 User 1 6 User 1 7 User 1 Note: All address lines not specified in the above table must be 0 when accessing the Protection Register—for example 21– 8 ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Word-Wide Protection Register Addressing ...

Page 68

... Package Body Thickness Ball Lead Diameter Package Body Length – 16-Mbit/2-Mbit Package Body Length – 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Package Body Length – 32-Mbit/8-Mbit Package Body Width – 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family ...

Page 69

... Seating Plane Coplanarity Corner to Ball A1 Distance Along E 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit Corner to Ball A1 Distance Along D 16-Mbit/2-Mbit Corner to Ball A1 Distance Along D 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Corner to Ball A1 Distance Along D 32-Mbit/8-Mbit ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Millimeters Sym Min Nom e 0.800 ...

Page 70

... Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb Corner to Ball A1 Distance Along D 16/02-Mb, 16/04-Mb Corner to Ball A1 Distance Along D 32/04-Mb, 32/08-Mb ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 70 Millimeters Sym Min Nom A 0.200 A1 ...

Page 71

... C3 SCSP Flash Memory F.9 Media Information Device Pin 1 Note: Top view, ball side down. Drawing is not to scale and is only designed to show orientation of devices. ® Datasheet Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family Tray Chamfer Order Number: 252636, Revision: 004 26 Aug 2005 71 ...

Page 72

... C3 SCSP Flash Memory Figure 21. SCSP Device Tape ( and mm) Note: Top view, ball side down. ® 26 Aug 2005 Intel Advanced+ Boot Block Flash Memory (C3) SCSP Family 72 Order Number: 252636, Revision: 004 Device Pin 1 Datasheet ...

Page 73

... Representative 297874 Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools. ...

Page 74

... Ordering Information for Product Combinations with 0.25 µm to 0.13 µm Flash Package RD = Leaded Ball Stacked -CSP PF = Lead-Free Ball Stacked-CSP Product Line Designator ® 28F or 38F = Intel Flash Memory Flash Density 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) SRAM Device Density 8 = x16 (8 Mbit) ...

Page 75

... C3 SCSP RD28F3208C3T70 RD28F3208C3B70 RD28F3208C3T90 No longer available. RD28F3208C3B90 RD28F3204C3T70 RD28F3204C3B70 RD28F1604C3T90 RD28F1604C3B90 RD28F1604C3T110 RD28F1604C3B110 RD28F1602C3T70 RD28F1602C3T90 RD28F1602C3B70 RD28F1602C3B90 RD28F1602C3T110 RD28F1602C3B110 Order Number: 252636, Revision: 004 0.13µm C3 SCSP RD38F1010C0ZTL0 RD38F1010C0ZBL0 PF38F1010C0ZTL0 PF38F1010C0ZBL0 RD38F1020C0ZTL0 RD38F1020C0ZBL0 PF28F1602C3TD70 RD28F1602C3TD70 RD28F1602C3BD70 RD28F1604C3TD70 RD28F1604C3BD70 26 Aug 2005 75 ...

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