RD38F1020C0ZBL0 Intel, RD38F1020C0ZBL0 Datasheet - Page 23

• Manufacturer Part Number: RD38F1020C0ZBL0
• Manufacturer: Intel

Specifications of RD38F1020C0ZBL0

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 8.
3.8
3.8.1
Datasheet
Notes:
1.
2.
3.
4.
5.
6.
WP#
0
1
0
1
0
1
1
DQ
In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ
current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ
indicates if a block is locked (1) or unlocked (0). DQ
At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the recommended
default.
The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled
(No) in that block’s current locking state.
The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock,
Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would mean that writing the command to
a block in the current locking state would change it to [001].
The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the
Intel factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs
to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.
“–” indicates no change in the current state.
0
0
0
0
1
1
1
1
Current State
DQ
Block Locking State Transitions
128 Bit Protection Register
The C3 SCSP architecture includes a 128-bit protection register than can be used to increase the
security of a system design. For example, the number contained in the protection register can be
used to “mate” the flash component with other system components such as the CPU or ASIC,
preventing device substitution.
Reading the Protection Register
The protection register is read in the configuration read mode. The device is switched to this mode
by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses
shown in Appendix E retrieve the specified information. To return to read array mode, write the
Read Array command (FFh).
0
0
1
1
1
0
1
0
C3 SCSP Flash Memory
Locked (Default)
Intel
Locked-Down
Lock-Down
Unlocked
Unlocked
Disabled
Locked
Name
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Allowed?
Program
Erase/
Yes
Yes
Yes
No
No
No
No
1
indicates if a block has been locked-down (1) or not (0).
Go To [001]
Go To [101]
Go To [111]
Lock
–
–
–
-
Next State after Command Input
Go To [000]
Go To [100]
Go To [110]
Unlock
–
–
–
–
1
, and Z = DQ
Lock-Down
Go To [011]
Go To [011]
Go To [111]
Go To [111]
Go To [111]
26 Aug 2005
0
, DQ
0
–
–
. The
1
). DQ
23
0