RD38F1020C0ZBL0 Intel, RD38F1020C0ZBL0 Datasheet - Page 44

• Manufacturer Part Number: RD38F1020C0ZBL0
• Manufacturer: Intel

Specifications of RD38F1020C0ZBL0

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

C3 SCSP Flash Memory
Figure 13.
7.4
26 Aug 2005
44
SUBSTRATE
D3
E4
Typical Flash + SRAM Substrate Power and Ground Connections
Notes:
1.
2.
3.
4.
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while
also programming or erasing flash. In addition, F-CE#, S-CS1# and S-CS2 should not be enabled at
the same time. (See
a summary of recommended operating modes.) Simultaneous operation of the can be summarized
by the following:
•
•
SRAM read/write are during a Flash Program or Erase Operation are allowed.
Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus
contention).
Intel
Substrate connections refer to ballout locations shown in
page
0.1µf capacitors should be used with D9, D10, A10and E4.
Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS.
Some SRAM devices do not have a S-VSSQ; in this case, this pad is a VCC.
FLASH DIE
F-V
®
8.
Advanced+ Boot Block Flash Memory (C3) SCSP Family
PP
S-X
F-X
XX
Table 2 “Intel® Advanced+ Boot Block SCSP Ball Descriptions” on page 9
Order Number: 252636, Revision: 004
SRAM DIE
S-V
SS
Substrate connection to package ball
SRAM die bond pad connection
Flash die bond pad connection
S-V
S-V
S-V
CCQ
SSQ
CC
Figure 1 “66-Ball SCSP Package Ballout” on
F-V
F-V
F-V
F-V
SSQ
CCQ
SS
CC
D10
A10
A9
D9
H8
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