RD38F1020C0ZBL0 Intel, RD38F1020C0ZBL0 Datasheet - Page 20

• Manufacturer Part Number: RD38F1020C0ZBL0
• Manufacturer: Intel

Specifications of RD38F1020C0ZBL0

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

C3 SCSP Flash Memory
3.7
26 Aug 2005
20
SR.7 WRITE STATE MACHINE STATUS
SR.6 = ERASE-SUSPEND STATUS (ESS)
SR.5 = ERASE STATUS (ES)
SR.4 = PROGRAM STATUS (PS)
SR.3 = F-V
SR.2 = PROGRAM SUSPEND STATUS (PSS)
SR.1 = BLOCK LOCK STATUS
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Note:
1 = Ready (WSMS)
0 = Busy
1 = Erase Suspended
0 = Erase In Progress/Completed
1 = Error In Block Erase
0 = Successful Block Erase
1 = Error in Programming
0 = Successful Programming
1 = F-V
0 = F-V
1 = Program Suspended
0 = Program in Progress/Completed
1 = Prog/Erase attempted on a locked block; Operation
0 = No operation to locked blocks
aborted.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
PP
PP
PP
Low Detect, Operation Abort
OK
STATUS (VPPS)
Block Locking
The instant, individual block locking feature that allows any flash block to be locked or unlocked
with no latency, which enables instant code and data protection.
This locking offers two levels of protection. The first level allows software-only control of block
locking (useful for data blocks that change frequently), while the second level requires hardware
interaction before locking can be changed (useful for code blocks that change infrequently).
The following sections will discuss the operation of the locking system. The term “state [XYZ]”
will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ
the Block Lock status register, and Z = bit DQ
Locking State Transitions” on page 23
Bit Number
Intel
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Check Write State Machine bit first to determine Word Program or
Block Erase completion, before checking Program or Erase Status
bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to 1. ESS bit remains set to 1 until an
Erase Resume command is issued.
When this bit is set to 1, WSM has applied the max. number of
erase pulses and is still unable to verify successful block erasure.
When this bit is set to 1, WSM has attempted but failed to program
a word/byte.
The F-V
level. The WSM interrogates F-V
Erase command sequences have been entered, and informs the
system if F-V
checked before the operation is verified by the WSM. The F-V
status bit is not guaranteed to report accurate feedback between
V
When Program Suspend is issued, WSM halts execution and sets
both WSMS and PSS bits to 1. PSS bit remains set to 1 until a
Program Resume command is issued.
If a program or erase operation is attempted to one of the locked
blocks, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
This bit is reserved for future use and should be masked out when
polling the status register.
defines all of these possible locking states.
PPLK
and V
PP
0
of the Block Lock status register.
status bit does not provide continuous indication of V
PP1
PP
has not been switched on. The F-V
min.
NOTES:
PP
level only after the Program or
Table 8 “Block
PP
Datasheet
is also
PP
1
PP
of