RD38F1020C0ZBL0 Intel, RD38F1020C0ZBL0 Datasheet - Page 13

• Manufacturer Part Number: RD38F1020C0ZBL0
• Manufacturer: Intel

Specifications of RD38F1020C0ZBL0

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2.1.3
2.1.4
2.1.5
Datasheet
When F-CE# and S-CS1# or S-CS
substantially reduces device power consumption. In standby mode, outputs are placed in a high-
impedance state independent of F-OE# and S-OE#. If the flash memory device is deselected during
a program or erase operation, the flash memory continues to consume active power until the
program or erase operation is complete.
Flash Reset
The flash memory device enters a reset mode when RP# is driven low. In reset mode, internal
circuitry is turned off and outputs are placed in a high-impedance state.
After returning from reset, a time t
t
operation is restored.
If RP# is taken low during a block erase or program operation, the operation aborts and the
memory contents at the aborted location are no longer valid.
Write
Commands are written to the flash memory Command User Interface (CUI), using standard
microprocessor write timings to control flash memory operations. The CUI does not occupy an
addressable memory location within the flash memory device. The address and data buses are
latched on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See
Figure 6 on page 33
Standby
PHEL
•
•
•
•
•
C3 SCSP Flash Memory
The flash memory device defaults to read array mode.
The status register is set to 80h.
The read configuration register defaults to asynchronous reads.
Writes to flash memory occur when both F-CE# and F-WE# are asserted and F-OE# is
deasserted.
Writes to SRAM occur when both S-CS1# and S-WE# are asserted and S-OE# and S-CS2 are
deasserted.
) is required before a write sequence can be initiated. After this wake-up interval, normal
Intel
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
and
Figure 7 on page 35
2
PHQV
are deasserted, the SCSP enters a standby mode, which
is required until outputs are valid. A delay (t
for read and write waveforms.)
26 Aug 2005
PHWL
or
13