RD38F1020C0ZBL0 Intel, RD38F1020C0ZBL0 Datasheet - Page 18

• Manufacturer Part Number: RD38F1020C0ZBL0
• Manufacturer: Intel

Specifications of RD38F1020C0ZBL0

• Operating Supply Voltage (max): 3.3V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

C3 SCSP Flash Memory
Note:
3.6
3.6.1
26 Aug 2005
18
After the Program Resume command is written to the flash memory:
F-V
F-RP# must also remain at V
Block Erase (20h)
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If F-V
after the Erase Confirm command was issued, the WSM will not execute the erase sequence;
instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to
identify that F-V
After an erase operation, clear the status register (50h) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
Suspending and Resuming Erase (B0h/D0h)
An erase operation can take several seconds to complete, therefore, the Erase Suspend command is
provided to allow erase-sequence interruption in order to read data from, or program data to,
another block in memory. Once an erase sequence has started, writing the Erase Suspend command
to the CUI causes the device to suspend the erase sequence at a predetermined point in the erase
algorithm. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 5.7, “Flash Erase and Program Timings” on page 31.
When an erase operation has been suspended, a Word Program or Read operation can be performed
within any block, except the block that is in an erase suspend state. An erase operation cannot be
nested within another erase suspend operation.
A suspended erase operation cannot resume until the nested program operation has completed.
Read Array, Read Status Register, Clear Status Register, Read Identifier, CFI Query, Erase
Resume, are all valid commands during Erase Suspend. Additionally, Program, Program Suspend,
Program Resume, Lock Block, Unlock Block and Lock-Down Block are valid commands during
Erase Suspend.
To resume an erase suspend operation, issue the Resume command. The Resume command can be
written to any device address. When a program operation is nested within an Erase Suspend
operation and the Program Suspend command is issued, the device will suspend the program
•
•
•
PP
WSM continues the programming process.
Status register bits SR.2 and SR.7 are automatically cleared.
The flash memory device automatically outputs status register data when read (see
A, “Program/Erase
Intel
must remain at the same F-V
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
PP
supply voltage was not within acceptable limits.
Order Number: 252636, Revision: 004
Flowcharts”).
IH
.
PP
level used for program while in program suspend mode.
PP
was not within acceptable limits
Datasheet
Appendix