MT47H64M16HR-3:H Micron Technology Inc, MT47H64M16HR-3:H Datasheet - Page 32
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MT47H64M16HR-3:H
Manufacturer Part Number
MT47H64M16HR-3:H
Description
IC DDR2 SDRAM 1GBIT 84FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet
1.MT47H64M16HR-3H.pdf
(134 pages)
Specifications of MT47H64M16HR-3:H
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
135mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (64M x 16)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-TFBGA
Lead Free Status / RoHS Status
Compliant
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Quantity
Price
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Table 11: DDR2 I
Notes: 1–7 apply to the entire table
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
Parameter/Condition
Operating burst read current: All banks
open, continuous burst reads, I
4, CL = CL (I
t
is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switch-
ing
Burst refresh current:
FRESH command at every
CKE is HIGH, CS# is HIGH between valid com-
mands; Other control and address bus inputs
are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read
current: All bank interleaving reads, I
0mA; BL = 4, CL = CL (I
t
t
HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs
are switching; See on page for details
RAS MAX (I
CK (I
RRD (I
DD
DD
);
),
t
CK =
t
DD
RCD =
DD
), AL = 0;
),
t
CK (I
t
RP =
t
RCD (I
DD
DD
Notes:
t
DD
RP (I
Specifications and Conditions (Die Revision H) (Continued)
),
t
CK =
t
), AL =
t
DD
CK =
RC =
t
RFC (I
DD
); CKE is HIGH, CS# is
t
); CKE is HIGH, CS#
CK (I
t
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
OUT
CK (I
RC (I
t
DD
RCD (I
UDQS#. I
tion devices when operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
DD
) interval;
DD
DD
DD1
= 0mA; BL =
DD
C
DD
DD
),
≤ 0°C
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
); RE-
OUT
),
= +1.8V ±0.1V, V
DD
t
RAS =
DD4R
t
) - 1 ×
RRD =
=
DD
, and I
I
ed by 2%; and I
values must be met with all combinations of EMR bits 10 and 11.
DD2P
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
IN
IN
DD
DD
DD7
≤ V
≥ V
and I
Symbol
values must be derated (I
I
conditions:
I
I
I
I
DD4R
DD6L
IL(AC)max
IH(AC)min
DD5
DD6
DD7
require A12 in EMR to be enabled during testing.
DDQ
DD3P(SLOW)
REF
= +1.8V ±0.1V, V
32
= V
DD6
Configuration
Electrical Specifications – I
DDQ
x4, x8, x16
and I
must be derated by 4%; I
x4, x8
x4, x8
x4, x8
/2
x16
x16
x16
DD7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
must be derated by 7%
DDL
DD
1Gb: x4, x8, x16 DDR2 SDRAM
= +1.8V ±0.1V, V
limits increase) on IT-option and AT-op-
-187E
150
190
180
210
250
300
7
5
C
DD4R
≤ 85°C:
-25E/
120
150
145
150
210
260
-25
© 2004 Micron Technology, Inc. All rights reserved.
7
5
REF
and I
= V
DD5W
DD
DDQ
-3E/
110
125
140
145
185
230
Parameters
/2.
must be derat-
-3
7
5
C
≤ +85°C.
Units
mA
mA
mA
mA