NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 342

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.7
9.7.1
342
Processor Interface Registers
NMI_SC—NMI Status and Control Register
I/O Address:
Default Value:
Lockable:
Bit
7
6
5
4
3
2
1
0
SERR# NMI Source Status (SERR#_NMI_STS) — RO.
1 = PCI agent detected a system error and pulses the PCI SERR# line. This interrupt source is
IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.
1 = An ISA agent (via SERIRQ) asserted IOCHK# on the ISA bus. This interrupt source is enabled
Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current state of the
8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a
determinate value. When writing to port 61h, this bit must be a 0.
Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or 1 to 0 at a
rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a
0.
IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.
0 = Enabled.
1 = Disabled and cleared.
PCI SERR# Enable (PCI_SERR_EN) — R/W.
0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable (SPKR_DAT_EN) — R/W.
0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.
0 = Disable
1 = Enable
enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing
to port 61h, this bit must be 0.
by setting bit 3 to 0. To reset the interrupt, set bit 3 to 0 and then set it to 1. When writing to port
61h, this bit must be a 0.
61h
00h
No
Description
Attribute:
Size:
Power Well:
Intel
R/W, RO
8 bit
Core
®
82801DB ICH4 Datasheet