NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 379

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

9.10.2
9.10.3
Intel
®
82801DB ICH4 Datasheet
GP_LVL—GPIO Level for Input or Output Register
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address:
Default Value:
Lockable:
Offset Address:
Default Value:
Lockable:
31:29, 26
31:29, 26
28:27,
28:27
25:24
23:16
25:24
23:16
15:0
15:0
Bit
Bit
Reserved
GPIO[n]_SEL — R/W.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Always 0. The GPIOs are fixed as outputs.
Always 1. These GPIOs are fixed as inputs.
Reserved
GP_LVL[n]
GP_IO_SEL register) then the bit can be updated by software to drive a high or low value on the
output pin. If GPIO[n] is programmed as an input, then software can read the bit to determine the
level on the corresponding input pin. These bits correspond to GPIO that are in the Resume well,
and will be reset to their default values by RSMRST# and also by a write to the CF9h register.
0 = Low
1 = High
GP_LVL[n]
output pin. These bits correspond to GPIO that are in the core well, and will be reset to their
default values by PCIRST#.
0 = Low
1 = High
Reserved. GPI[13:11], and [8:0] the active status of a GPI is read from the corresponding bit in
GPE0_STS register.
GPIOBASE +04h
0000FFFFh
No
GPIOBASE +0Ch
1B3F 0000h
No
—
—
R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in the
R/W. These bits can be updated by software to drive a high or low value on the
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
Resume
R/W, RO
32-bit
See bit descriptions
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