NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 62

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Intel
62
Table 3-4. Power Plane and States for Output and I/O Signal (Sheet 4 of 4)
®
ICH4 Power Planes and Pin States
NOTES:
1. ICH4 sets these signals at reset for processor frequency strap.
2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH4 comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH4’s VRMPWRGD and
4. The states of main I/O signals are taken at the times During PCIRST# and Immediately after PCIRST#.
5. The states of resume I/O signals are taken at the times During RSMRST# and Immediately after RSMRST#.
6. SLP_5# is high in the S4 state and asserted low in the S5 state.
7. SUSCLK is running during PCIRST#, but is driven low during RSMRST#.
GPIO[18]
GPIO[19:20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[27:28]
GPIO[32:43]
PWROK signals, and thus will be driven low by ICH4 when either VRMPWRGD or PWROK are inactive.
During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to
High-Z.
Signal Name
Resume I/O
Resume I/O
Resume I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Power
Plane
RSMRST#
PCIRST#
Unmuxed GPIO Signals
During
High-Z
High
High
High
High
High
High
High
Low
4
5,7
/
Immediately
PCIRST#
RSMRST#
See Note 2
High-Z
after
High
High
High
High
High
High
Low
4
5
/
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Intel
S1
®
82801DB ICH4 Datasheet
Defined
Defined
Defined
Off
Off
Off
S3
Off
Off
Off
Defined
Defined
Defined
S4/S5
Off
Off
Off
Off
Off
Off