NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 7

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Intel
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82801DB ICH4 Datasheet
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.9.5
Real Time Clock (D31:F0) ...........................................................................127
5.10.1 Update Cycles.................................................................................127
5.10.2 Interrupts.........................................................................................128
5.10.3 Lockable RAM Ranges ...................................................................128
5.10.4 Century Rollover .............................................................................128
5.10.5 Clearing Battery-Backed RTC RAM................................................128
Processor Interface (D31:F0).......................................................................130
5.11.1 Processor Interface Signals ............................................................130
5.11.2 Dual-Processor Designs .................................................................132
5.11.3 Speed Strapping for Processor.......................................................134
Power Management (D31:F0)......................................................................135
5.12.1 Intel
5.12.2 System Power Planes.....................................................................137
5.12.3 Intel
5.12.4 SMI#/SCI Generation......................................................................137
5.12.5 Dynamic Processor Clock Control ..................................................139
5.12.6 Sleep States....................................................................................141
5.12.7 Thermal Management.....................................................................145
5.12.8 Event Input Signals and Their Usage .............................................146
5.12.9 ALT Access Mode...........................................................................148
5.12.10 System Power Supplies, Planes, and Signals ................................151
5.12.11 Clock Generators ............................................................................152
5.12.12 Legacy Power Management Theory of Operation ..........................153
System Management (D31:F0)....................................................................154
5.13.1 Theory of Operation ........................................................................154
5.13.2 Alert on LAN* ..................................................................................155
General Purpose I/O ....................................................................................159
5.14.1 GPIO Mapping ................................................................................159
5.14.2 Power Wells ....................................................................................161
5.14.3 SMI# and SCI Routing ....................................................................161
IDE Controller (D31:F1) ...............................................................................161
5.15.1 PIO Transfers..................................................................................162
5.15.2 Bus Master Function .......................................................................164
5.15.3 Ultra ATA/33 Protocol .....................................................................168
5.15.4 Ultra ATA/66 Protocol .....................................................................170
5.15.5 Ultra ATA/100 Protocol ...................................................................170
5.15.6 Ultra ATA/33/66/100 Timing............................................................171
5.15.7 IDE Swap Bay.................................................................................171
USB UHCI Controllers (D29:F0, F1 and F2)................................................172
5.16.1 Data Structures in Main Memory ....................................................172
5.16.2 Data Transfers to/from Main Memory .............................................178
5.16.3 Data Encoding and Bit Stuffing .......................................................184
5.16.4 Bus Protocol....................................................................................184
5.16.5 Packet Formats...............................................................................187
5.16.6 USB Interrupts ................................................................................189
5.16.7 USB Power Management ...............................................................192
5.16.8 USB Legacy Keyboard Operation...................................................192
USB EHCI Controller (D29:F7) ....................................................................195
5.17.1 EHC Initialization.............................................................................195
5.17.2 Data Structures in Main Memory ....................................................196
Data Frame Format.........................................................................126
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ICH4 and System Power States............................................135
ICH4 Power Planes...............................................................137
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