NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 395

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

10.1.24
Intel
®
82801DB ICH4 Datasheet
IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)
Address Offset:
Default Value:
31:20
19:18
17:16
9: 8
Bit
15
14
13
12
11
10
7
6
Reserved
SEC_SIG_MODE — R/W. These bits are used to control the mode of the Secondary IDE signal
pins. If the SRS bit (bit 7, offset D5h of D31:F0) is 1, the reset states of bits 19:18 will be 01 (tri-
state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
PRIM_SIG_MODE — R/W. These bits are used to control the mode of the Primary IDE signal pins.
If the PRS bit (bit 6, offset D5h of D31:F0) is 1, then the reset states of bits 17:16 will be 01
(tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in conjunction with
the SCT1 bits to enable/disable Ultra ATA/100 timings for the Secondary Slave drive.
0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.
1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register).
Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in conjunction with
the SCT0 bits to enable/disable Ultra ATA/100 timings for the Secondary Master drive.
0 = Disable Ultra ATA/100 timing for the Secondary Master drive.
1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register).
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in conjunction with the
PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in conjunction with the
PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).
Reserved
WR_PingPong_EN — R/W.
0 = Disabled. The buffer behaves similar to PIIX4.
1 = Enables the write buffer to be used in a split (ping/pong) manner.
Reserved
Secondary Slave Channel Cable Reporting — R/W. BIOS should program this bit to tell the IDE
driver which cable is plugged into the channel.
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
Secondary Master Channel Cable Reporting — R/W. Same description as bit 7
54h
00h
Description
Attribute:
Size:
IDE Controller Registers (D31:F1)
R/W
32 bits
395