NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 396

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1)
10.2
396
Table 10-2. Bus Master IDE I/O Registers
Bus Master IDE I/O Registers (D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers
can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an
indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be
attempted). The description of the I/O registers is shown below in
0C–0F
Offset
04–07
Bit
5
4
3
2
1
0
00
01
02
03
08
09
0A
0B
Primary Slave Channel Cable Reporting — R/W. Same description as bit 7
Primary Master Channel Cable Reporting — R/W. Same description as bit 7
Secondary Drive 1 Base Clock (SCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Secondary Drive 0 Base Clock (SCBO) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 1 Base Clock (PCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 0 Base Clock (PCB0) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Mnemonic
BMICP
BMISP
BMIDP
BMICS
BMISS
BMIDS
Bus Master IDE Command Primary
Reserved
Bus Master IDE Status Primary
Reserved
Bus Master IDE Descriptor Table Pointer Primary
Bus Master IDE Command Secondary
Reserved
Bus Master IDE Status Secondary
Reserved
Bus Master IDE Descriptor Table Pointer Secondary
Register Name
Description
Table
Intel
®
10-2.
82801DB ICH4 Datasheet
xxxxxxxxh
xxxxxxxxh
Default
00h
00h
00h
00h
00h
00h
00h
00h
R/WC, R/W,
R/WC, R/W,
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO