FW82801EB S L73Z Intel, FW82801EB S L73Z Datasheet - Page 310

• Manufacturer Part Number: FW82801EB S L73Z
• Manufacturer: Intel

Specifications of FW82801EB S L73Z

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.20
8.1.21
8.1.22
8.1.23
310
PREF_MEM_MLT—Prefetchable Memory Limit Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
IOBASE_HI—I/O Base Upper 16 Bits Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
IOLIM_HI—I/O Limit Upper 16 Bits Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
INT_LN—Interrupt Line Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:4
15:0
15:0
Bit
3:0
Bit
Bit
Bit
7:0
Prefetchable Memory Address Limit
prefetchable memory address range for PCI. These 12 bits correspond to address bits 31:20.
Reserved.
I/O Address Base Upper 16 bits [31:16] — RO. Not supported; hardwired to 0.
I/O Address Limit Upper 16 bits [31:16] — RO. Not supported; hardwired to 0.
Interrupt Line Routing (INT_LN) — RO. Hardwired to 00h. The bridge does not generate interrupts,
and interrupts from downstream devices are routed around the bridge.
26
0000h
30
0000h
32
0000h
3Ch
00h
–
–
–
27h
31h
33h
—
RW. This field defines the limit address of the
Description
Description
Description
Description
Intel
Attribute:
Size:
Attribute:
Size:
Attribute:
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Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16-bit
RO
16 bits
RO
16 bits
RO
8 bits