FW82801EB Intel, FW82801EB Datasheet

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FW82801EB

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FW82801EB
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Intel
Datasheet

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®
Intel
82801EB I/O Controller
®
Hub 5 (ICH5) / Intel
82801ER
I/O Controller Hub 5 R (ICH5R)
Datasheet
April 2003
Document Number: 252516-001

FW82801EB Summary of contents

Page 1

... Intel 82801EB I/O Controller Hub 5 (ICH5) / Intel I/O Controller Hub 5 R (ICH5R) Datasheet April 2003 ® 82801ER Document Number: 252516-001 ...

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... Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM. Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

Page 3

... Timers Based on 82C54 I — System timer, Refresh request, Speaker tone output ® The Intel ICH5 / ICH5R may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet New: Integrated 1 ...

Page 4

... USB 2.0 IDE-Primary Intel ® 82801EB IDE-Secondary ICH5 or Intel ® 82801ER ICH5R LAN Connect GPIO LPC I/F Super I/O Other ASICs (Optional) ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Power Management Clock Generators System Management (TCO) SMBus 2.0 PCI Bus S S LAN ...

Page 5

... Output and I/O Signals Planes and States .........................................................................71 3.5 Power Planes for Input Signals...........................................................................................75 ® 4 Intel ICH5 and System Clock Domains....................................................................................77 5 Functional Description................................................................................................................79 5.1 Hub Interface to PCI Bridge (D30:F0).................................................................................79 5.1.1 PCI Bus Interface...................................................................................................79 5.1.2 PCI-to-PCI Bridge Model .......................................................................................80 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 5 ...

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... SYNC Time-Out ................................................................................... 106 5.4.1.7 SYNC Error Indication.......................................................................... 106 5.4.1.8 LFRAME# Usage ................................................................................. 107 5.4.1.9 I/O Cycles ............................................................................................ 108 5.4.1.10 Bus Master Cycles ............................................................................... 108 5.4.1.11 LPC Power Management..................................................................... 108 5.4.1.12 Configuration and Intel 6 ® ICH5 Implications ......................................... 108 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... Modes of Operation .............................................................................................126 5.8.4.1 Fully Nested Mode ...............................................................................126 5.8.4.2 Special Fully-Nested Mode ..................................................................127 5.8.4.3 Automatic Rotation Mode (Equal Priority Devices) ..............................127 5.8.4.4 Specific Rotation Mode (Specific Priority)............................................127 5.8.4.5 Poll Mode .............................................................................................127 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 7 ...

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... Power Management............................................................................. 144 5.12.3 Speed Strapping for Processor............................................................................ 144 5.13 Power Management (D31:F0) .......................................................................................... 146 5.13.1 Features............................................................................................................... 146 ® 5.13.2 Intel ICH5 and System Power States ................................................................ 146 5.13.3 System Power Planes.......................................................................................... 148 ® 5.13.4 Intel ICH5 Power Planes ................................................................................... 148 5.13.5 SMI#/SCI Generation........................................................................................... 148 8 ® ...

Page 9

... General Purpose I/O .........................................................................................................170 5.15.1 GPIO Mapping .....................................................................................................170 5.15.2 Power Wells .........................................................................................................173 5.15.3 SMI# and SCI Routing .........................................................................................173 5.16 IDE Controller (D31:F1) ....................................................................................................174 5.16.1 PIO Transfers ......................................................................................................174 5.16.1.1 IDE Port Decode ..................................................................................174 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 9 ...

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... Standard ATA Emulation ..................................................................... 185 5.17.1.2 48-Bit LBA Operation ........................................................................... 185 5.17.2 Hot Swap Operation ............................................................................................ 186 ® 5.17.3 Intel RAID Technology Configuration (Intel 5.17.3.1 Intel 5.17.4 Power Management Operation............................................................................ 186 5.17.4.1 Power State Mappings......................................................................... 186 5.17.4.2 Power State Transitions....................................................................... 187 5.17.4.3 SMI Trapping (APM) ............................................................................ 188 5 ...

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... USB 2.0 Legacy Keyboard Operation..................................................................225 5.20.10 USB 2.0 Based Debug Port .................................................................................226 5.20.10.1 Theory of Operation ............................................................................226 5.21 SMBus Controller (D31:F3) ..............................................................................................231 5.21.1 Host Controller .....................................................................................................231 5.21.1.1 Command Protocols ............................................................................232 2 5.21.1.2 I ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet C Behavior.........................................................................................242 Contents 11 ...

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... Contents 5.21.2 Bus Arbitration ..................................................................................................... 243 5.21.3 Bus Timing........................................................................................................... 243 5.21.3.1 Clock Stretching................................................................................... 243 5.21.3.2 Bus Time Out (Intel 5.21.4 Interrupts / SMI# .................................................................................................. 244 5.21.5 SMBALERT# ....................................................................................................... 245 5.21.6 SMBus CRC Generation and Checking............................................................... 245 5.21.7 SMBus Slave Interface ........................................................................................ 245 5.21.7.1 Format of Slave Write Cycle ................................................................ 246 5 ...

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... Controller—B1:D8:F0) ................................................................................283 7.1.20 CAP_ID — Capability Identification Register (LAN Controller—B1:D8:F0) ................................................................................283 7.1.21 NXT_PTR — Next Item Pointer Register (LAN Controller—B1:D8:F0) ................................................................................284 7.1.22 PM_CAP — Power Management Capabilities Register (LAN Controller—B1:D8:F0) ................................................................................284 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 13 ...

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... PCISTS—PCI Status Register (HUB-PCI—D30:F0) ............................................................................................ 304 8.1.5 RID—Revision Identification Register (HUB-PCI—D30:F0) ............................................................................................ 305 8.1.6 SCC—Sub-Class Code Register (HUB-PCI—D30:F0) ............................................................................................ 305 8.1.7 BCC—Base-Class Code Register (HUB-PCI—D30:F0) ............................................................................................ 305 14 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0) ............................................................................................315 8.1.29 PCI_MAST_STS—PCI Master Status Register (HUB-PCI—D30:F0) ............................................................................................315 8.1.30 ERR_CMD—Error Command Register (HUB-PCI—D30:F0) ............................................................................................316 8.1.31 ERR_STS—Error Status Register (HUB-PCI—D30:F0) ............................................................................................316 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 15 ...

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... I/F — D31:F0)............................................................................................. 330 9.1.23 GEN_STA—General Status Register (LPC I/F—D31:F0)............................................................................................... 332 9.1.24 BACK_CNTL—Backed Up Control Register (LPC I/F—D31:F0)............................................................................................... 333 9.1.25 RTC_CONF—Real Time Clock Configuration Register (LPC I/F—D31:F0)............................................................................................... 334 16 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... I/F—D31:F0) ...............................................................................................352 9.3.1.1 RDBK_CMD—Read Back Command (LPC I/F—D31:F0) ...............................................................................353 9.3.1.2 LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0) ...............................................................................353 9.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register (LPC I/F—D31:F0) ...............................................................................................354 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 17 ...

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... RTC_REGA—Register A (LPC I/F—D31:F0)............................................................................................... 370 9.6.3 RTC_REGB—Register B (General Configuration) (LPC I/F—D31:F0)............................................................................................... 371 9.6.4 RTC_REGC—Register C (Flag Register) (LPC I/F—D31:F0)............................................................................................... 372 9.6.5 RTC_REGD—Register D (Flag Register) (LPC I/F—D31:F0)............................................................................................... 372 18 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... STPCLK_DEL—Stop Clock Delay Register (PM—D31:F0)......................................................................................................380 9.8.5 USB_TDD—USB Transient Disconnect Detect (PM—D31:F0)......................................................................................................380 9.8.6 SATA_RD_CFG—SATA RAID Configuration (PM—D31:F0) - (Intel 9.8.7 GPI_ROUT—GPI Routing Control Register (PM—D31:F0)......................................................................................................381 9.8.8 TRP_FWD_EN—IO Monitor Trap Forwarding Enable Register (PM—D31:F0) .......................................................................................382 9.8.9 MON[n]_TRP_RNG— ...

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... Register (IDE—D31:F1)....................................................................................... 420 10.1.11 PCNL_BAR—Primary Control Block Base Address Register (IDE—D31:F1) ..................................................................................................... 421 10.1.12 SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1) ......................................................................................... 421 10.1.13 SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1) ......................................................................................... 421 20 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 21

... PMLT—Primary Master Latency Timer Register (SATA–D31:F2) ...................................................................................................438 11.1.10 PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2) .....................................................................................438 11.1.11 PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) ...................................................................................................439 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 21 ...

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... SRD—SATA Registers Data (SATA–D31:F2) ................................................................................................... 452 11.1.36 SIRA—SATA Initialization Register A (SATA–D31:F2) ....................................... 452 11.1.37 SIRB — SATA Initialization Register B (SATA–D31:F2) ..................................... 453 11.1.38 PMR0 — Power Management Register Port 0 (SATA–D31:F2) ................................................................................................... 453 22 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... INT_LN—Interrupt Line Register (USB—D29:F0/F1/F2/F3) ....................................................................................466 12.1.14 INT_PN—Interrupt Pin Register (USB—D29:F0/F1/F2/F3) ....................................................................................467 12.1.15 USB_RELNUM—Serial Bus Release Number Register (USB—D29:F0/F1/F2/F3) ....................................................................................467 12.1.16 USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register (USB—D29:F0/F1/F2/F3)......................................................................468 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 23 ...

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... Register (USB EHCI—D29:F7)............................................................................ 486 13.1.17 NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—D29:F7) .......................................................................................... 486 13.1.18 PWR_CAP—Power Management Capabilities Register (USB EHCI—D29:F7) .......................................................................................... 487 13.1.19 PWR_CNTL_STS—Power Management Control/Status Register (USB EHCI—D29:F7)............................................................................ 488 24 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... Capability Register (USB EHCI—D29:F7) ...........................................................491 13.1.27 LEG_EXT_CS—USB EHCI Legacy Support Extended Control / Status Register (USB EHCI—D29:F7) ..................................................492 13.1.28 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register (USB EHCI—D29:F7) ..........................................................................................493 13.1.29 ACCESS_CNTL—Access Control Register (USB EHCI—D29:F7) ..........................................................................................495 13 ...

Page 26

... AUX_CTL—Auxiliary Control Register (SMBUS—D31:F3) .............................................................................................. 528 14.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register (SMBUS—D31:F3) .............................................................................................. 528 14.2.14 SMBUS_PIN_CTL—SMBUS Pin Control Register (SMBUS—D31:F3) .............................................................................................. 529 14.2.15 SLV_STS—Slave Status Register (SMBUS—D31:F3) .............................................................................................. 529 26 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... INT_LN—Interrupt Line Register (Audio—D31:F5) ..................................................................................................541 15.1.18 INT_PN—Interrupt Pin Register (Audio—D31:F5) ..................................................................................................542 15.1.19 PCID—Programmable Codec Identification Register (Audio—D31:F5) ..................................................................................................542 15.1.20 CFG—Configuration Register (Audio—D31:F5) ..................................................................................................543 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 27 ...

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... SCC—Sub Class Code Register (Modem—D31:F6) ............................................................................................... 563 16.1.8 BCC—Base Class Code Register (Modem—D31:F6) ............................................................................................... 563 16.1.9 HEADTYP—Header Type Register (Modem—D31:F6) ............................................................................................... 563 16.1.10 MMBAR—Modem Mixer Base Address Register (Modem—D31:F6) ............................................................................................... 564 28 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... GEN_CONF—General Configuration Register.................................................................581 17.3 GINTR_STA—General Interrupt Status Register .............................................................582 17.4 MAIN_CNT—Main Counter Value Register......................................................................582 17.5 TIMn_CONF—Timer n Configuration and Capabilities Register .........................................................................................................583 17.6 TIMn_COMP—Timer n Comparator Value Register ........................................................585 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 29 ...

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... Timing Diagrams............................................................................................................... 619 20 Package Information ................................................................................................................. 629 21 Testability................................................................................................................................... 631 21.1 Test Mode Description...................................................................................................... 631 21.2 Tri-State Mode .................................................................................................................. 632 21.3 XOR Chain Mode.............................................................................................................. 632 21.3.1 XOR Chain Testability Algorithm Example .......................................................... 632 A Register Index............................................................................................................................ 639 B Register Bit Index ...................................................................................................................... 661 30 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

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... EEPROM Read Instruction Waveform.........................................................................96 10 LPC Interface Diagram .............................................................................................................103 11 Typical Timing for LFRAME#....................................................................................................107 12 Abort Mechanism......................................................................................................................107 ® 13 Intel ICH5 DMA Controller ......................................................................................................109 14 DMA Serial Channel Passing Protocol .....................................................................................113 15 DMA Request Assertion through LDRQ# .................................................................................116 16 Coprocessor Error Timing Diagram ..........................................................................................142 17 Signal Strapping ...

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... Power Sequencing and Reset Signal Timings ......................................................................... 625 21 G3 (Mechanical Off Timings ......................................................................................... 626 Timing .............................................................................................................. 626 Timings ............................................................................................................. 627 24 AC’97 Data Input and Output Timings ...................................................................................... 627 ® 25 Intel ICH5 Package (Top and Side Views) ............................................................................. 629 ® 26 Intel ICH5 Package (Bottom View) ......................................................................................... 630 27 Test Mode Entry (XOR Chain Example)................................................................................... 631 28 Example XOR Chain Circuitry ...

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... Start Field Bit Definitions ..........................................................................................................104 35 Cycle Type Bit Definitions.........................................................................................................105 36 Transfer Size Bit Definition .......................................................................................................105 37 SYNC Bit Definition...................................................................................................................106 ® 38 Intel ICH5 Response to Sync Failures....................................................................................106 39 DMA Transfer Size ...................................................................................................................111 40 Address Shifting in 16-Bit I/O DMA Transfers ..........................................................................111 41 DMA Cycle vs. I/O Address ......................................................................................................115 42 PCI Data Bus vs ...

Page 34

... NMI Sources ............................................................................................................................. 143 56 DP Signal Differences .............................................................................................................. 143 57 Frequency Strap Behavior Based on Exit State ....................................................................... 144 58 Frequency Strap Bit Mapping ................................................................................................... 145 59 General Power States for Systems Using Intel 60 State Transition Rules for Intel 61 System Power Plane ................................................................................................................ 148 62 Causes of SMI# and SCI .......................................................................................................... 149 63 Sleep Types.............................................................................................................................. 152 64 Causes of Wake Events ...

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... Output Tag Slot 0......................................................................................................................262 129 AC-link State during PCIRST#..................................................................................................264 130 PCI Devices and Functions ......................................................................................................268 131 Fixed I/O Ranges Decoded by Intel 132 Variable I/O Decode Ranges ....................................................................................................272 133 Memory Decode Ranges from Processor Perspective.............................................................273 134 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0).................................275 135 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ...

Page 36

... Modem Registers ..................................................................................................................... 569 174 Memory-Mapped Registers ...................................................................................................... 579 ® 175 Intel ICH5 Ballout by Signal Name ......................................................................................... 590 ® 176 Intel ICH5 Ballout by Ball Number .......................................................................................... 594 177 DC Current Characteristics....................................................................................................... 599 178 DC Characteristic Input Signal Association .............................................................................. 600 179 DC Input Characteristics........................................................................................................... 601 180 DC Characteristic Output Signal Association ........................................................................... 603 181 DC Output Characteristics ...

Page 37

... XOR Chain #4-2 (RTCRST# Asserted for 7 PCI Clocks While PWROK Active)......................637 ® 204 Intel ICH5 PCI Configuration Registers ..................................................................................639 ® 205 Intel ICH5 Fixed I/O Registers ................................................................................................650 ® 206 Intel ICH5 Variable I/O Registers ...........................................................................................655 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Contents 37 ...

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... Contents Revision History Revision -001 Initial release 38 Description ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Date April 2003 ...

Page 39

... This manual is intended for Original Equipment Manufacturers and BIOS vendors creating ® Intel 82801EB ICH5 and Intel manual, all references to ICH5 refer to both ICH5 and ICH5R components, unless specifically noted otherwise. This manual assumes a working knowledge of the vocabulary and principles of USB, IDE, SATA, AC ’97, SMBus, PCI, ACPI and LPC. Although some details of these features are described within this manual, refer to the individual industry specifications listed in the complete details ...

Page 40

... Open Drain, etc.) of all signals. ® Chapter 3. Intel Chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. ...

Page 41

... Chapter 21. Testability Chapter 21 provides detail about the implementation of test modes provided in the ICH5. Index This manual ends with indexes of registers and register bits. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Introduction 41 ...

Page 42

... PCI to LPC Bridge IDE Controller New: SATA Controller SMBus Controller AC’97 Audio Controller AC’97 Modem Controller USB UHCI Controller #1 USB UHCI Controller #2 USB UHCI Controller #3 New: USB UHCI Controller #4 USB 2.0 EHCI Controller LAN Controller ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet 2 C ...

Page 43

... Revision 1.1. The Low Pin Count (LPC) Bridge function of the ICH5 resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Introduction Section 5.16 43 ...

Page 44

... The ICH5 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and low-speed capable. ICH5’s port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller. See 44 Section 5.19 and Section 5.20 for details. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 45

... Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Introduction Section 5.2 for ...

Page 46

... SMI# or TCO interrupt due to an active INTRUDER# signal. • SMBus 2.0. The ICH5 integrates an SMBus controller that provides an interface to manage peripherals (e.g., serial presence detection (SPD) and thermal sensors) with host notify capabilities. 46 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 47

... AC-link. By using an audio codec, the AC-link allows for cost-effective, high-quality, integrated audio on Intel’s chipset-based platform. In addition ’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC ’97. The ICH5-integrated digital link allows several external codecs to be connected to the ICH5. The system designer can provide audio with an audio codec, a modem with a modem codec integrated audio/modem codec ...

Page 48

... Introduction 48 This page is intentionally left blank. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 49

... When “#” is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I Input Pin O Output Pin OD Open Drain Output Pin. I/O Bi-directional Input / Output Pin. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Signal Description 2 49 ...

Page 50

... Signal Description ® Figure 1. Intel ICH5 Interface Signals Block Diagram – – rfa rfa ria rfa rfa rru rfa rfa irm rfa rfa I rfa c e ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet I ...

Page 51

... O signals are multiplexed onto this pin. O EEPROM Shift Clock: This signal is the serial shift clock output to the EEPROM. EEPROM Data In: This signal transfers data from the EEPROM to the Intel I This signal has an integrated pull-up resistor. O EEPROM Data Out: This signal transfers data from the ICH5 to the EEPROM. ...

Page 52

... PCI Address/Data: AD[31:0] are the signals of the multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The Intel drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. ...

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... GNTB# / GPIO17# PCICLK ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Initiator Ready: IRDY# indicates the ICH5's ability Initiator, to complete the current data phase of the transaction used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. ...

Page 54

... Serial ATA 1 Differential Receive Pair: These are inbound high-speed I differential signals from Port 1. Serial ATA Resistor Bias: These are analog connection points for an external I resistor to ground. SATA Drive Activity Indicator: This signal indicates SATA drive activity when OD driven low. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Description Description ...

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... Primary and Secondary IDE Device DMA Acknowledge: These signals directly drive the DAK# signals on the primary and secondary IDE connectors. Each is ® asserted by the Intel ICH5 to indicate to IDE DMA slave devices that a given data O transfer cycle (assertion of DIOR# or DIOW DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel ...

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... LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to external Super I/O device. An internal pull-up resistor is provided on these signals. LDRQ1# may optionally be used as GPI. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Description Description ...

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... PIRQ[H:E]# / I/OD GPIO[5:2] IRQ[14:15] ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 10, 11, 12, 14 described in PIRQx# line has a separate Route Control register. ...

Page 58

... Data/Address/Command signals for ports 0 and 1. These ports can be routed to UHCI controller #1 or the EHCI controller. I/O NOTE: No external resistors are required on these signals. The Intel integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor Universal Serial Bus Port 3:2 Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3 ...

Page 59

... Hardware clock throttling mode. Can also generate an SMI SCI. Thermal Trip: When low, this signal indicates that a thermal trip from the processor ® occurred, and the Intel ICH5 will immediately transition state. The ICH5 will not wait for the processor stop grant cycle since the processor has overheated. ...

Page 60

... Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. Speed Strap: During the reset sequence, the Intel corresponding bit is set in the FREQ_STRP register. CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state ...

Page 61

... ASIC or LAN controller. External pull-ups are required. Note that SMLINK0 corresponds to an SMBus Clock signal, and SMLINK1 corresponds to an SMBus Data signal. SMLink Alert: This signal is an output from the Intel ASF or an external management controller in order for the LAN’s SMLINK slave to be serviced. ...

Page 62

... Test Point 0: This signal must have an external pull-up to VccSus3_3. O Test Point 1: This signal is not implemented and should be routed to a test point. O Test Point 2: This signal is not implemented and should be routed to a test point. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Description Description Description ...

Page 63

... I/O GPIO23 O GPIO22 OD GPIO21 O ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet O AC ’97 Reset: Master hardware reset to external codec(s ’97 Sync: 48 kHz fixed rate sample sync to the codec(s). AC ’97 Bit Clock: 12.288 MHz serial data clock generated by the external I Codec(s). This signal has an integrated pull-down resistor (see Note below). ...

Page 64

... Fixed as Input only. Main power well. Fixed as Input only. Main power well. Can be used instead as PIRQ[E:H]#. Fixed as Input only. Main power well. Can be used instead as PC/PCI REQ[A:B]#. GPIO1 can also alternatively be used for PCI REQ5#. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 65

... AC power is not available. NOTE: VccSus1_5_A 1. This voltage plane is generated internally 2. Do not connect the three sets of VccSus1_5_x signal groups on the Intel 1.5 V supply for resume well logic (3 pins). This power is not expected to be shut off unless AC power is not available. NOTE: VccSus1_5_B 1 ...

Page 66

... SPKR No Reboot 66 When Sampled The signal has a weak internal pull-down. If the signal is sampled high, the Intel Rising Edge of strap pins for safe mode. Refer to the processor PWROK specification for speed strapping definition. The status of this strap is readable via the SAFE_MODE bit (bit 2, D31: F0, Offset D4h) ...

Page 67

... V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not derive the VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform design. Figure 3. Example V5REF Sequencing Circuit ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Figure 2 1µF 100 kΩ ...

Page 68

... Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Table 24. Chapter 21 for a detailed Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 All “Z” Reserved. DO NOT ATTEMPT Long XOR Reserved. DO NOT ATTEMPT ...

Page 69

... Intel ICH5 Power Planes and Pin States 3.1 Power Planes ® Table 25. Intel ICH5 Power Planes Plane Main I/O (3.3 V) Main Logic (1.5 V) Resume I/O (3.3 V Standby) Resume Logic (1.5 V Standby) Processor I/F (0.8 ~ 1.75 V) RTC ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ® ...

Page 70

... Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Notes ...

Page 71

... Note that the signal levels are the same in S4 and S5. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ® Intel ICH5 Power Planes and Pin States Integrated Series Termination Resistor Value approximately 33 Ω (See Note) Tri-state. ICH5 not driving the signal high or low. ...

Page 72

... High-Z High-Z Main I/O Low Low Main I/O High High Main I/O High High Main I/O High High Main I/O High High ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet S4/S5 5 Defined Off Off Defined Off Off High-Z Off Off High-Z Off ...

Page 73

... USBRBIAS SLP_S3# SLP_S4# SLP_S5# SUS_STAT# SUSCLK A20M# CPUPWRGD CPUSLP# IGNNE# INIT# INTR NMI SMI# STPCLK# ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Intel During Immediately Power 4 PCIRST# / after PCIRST# Plane 5 RSMRST# RSMRST# SATA Interface Main I/O High-Z High-Z Main I/O High-Z ...

Page 74

... Low Low Resume I/O High High Resume I/O High High Resume I/O High High Main I/O High High Main I/O High High ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet S4/S5 5 Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Off ...

Page 75

... IRQ[15:14] LAN_CLK LAN_RST# LAN_RXD[2:0] LDRQ0# LDRQ1# OC[7:0]# PCICLK PDDREQ ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Intel Power Well Driver During Reset Main I/O External Microcontroller Main I/O AC ’97 Codec Resume I/O AC ’97 Codec Main I/O Clock Generator Main I/O Clock Generator ...

Page 76

... Resume I/O External Pull-Up Resume I/O External Circuit Main I/O Thermal Sensor CPU I/O Thermal Sensor Resume I/O External Pull-Down Main I/O Processor Voltage Regulator ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Static Low Low Driven Driven Driven Driven Driven Driven ...

Page 77

... Differential clock pair used for SATA. Generator Main Clock 66 MHz Hub I/F, Processor I/F. Shut off during S3 or below. Generator Free-running PCI Clock to the Intel Main Clock 33 MHz remains on during S0 and S1 state, and is expected to Generator be shut off during S3 or below. Main Clock PCI Bus, LPC I/F ...

Page 78

... Figure 4. Conceptual System Clock Diagram Intel ICH5 32 kHz XTAL 78 66 MHz 33 MHz Clock 14.31818 MHz Gen. 48 MHz  100 MHz Diff. Pair 12.288 MHz AC’97 Codec(s) 50 MHz LAN Connect SUSCLK# (32 kHz) ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet PCI Clocks (33 MHz) 14.31818 MHz 48 MHz ...

Page 79

... Special Cycle with the Shutdown message type. • Device Number (AD[15:11]) = 11111 • Function Number (AD[10:8]) = 111 • Register Number (AD[7:2]) = 000000 • Data = 00h • Bus number matches secondary bus number ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 5 79 ...

Page 80

... PCI devices. The conceptual logic diagrams in sources of SERR#, along with their respective enable and status bits. error reporting logic is configured for NMI# generation. 80 Figure 5 and Figure 6 Figure 7 shows how the ICH5 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet illustrate all ...

Page 81

... nable] D 30: eceived Target A bort Figure 6. Secondary Status Register Error Reporting Logic PCI Delayed Transaction Timeout D31:F0 D31_ERR_CFG [SERR_DTT_EN] LPC Device Signaling an Error IOCHK# via SERIRQ D31:F0 D31_ERR_CFG Received Target Abort ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet 30: 30: 30: D30:F0 BRIDGE_CNT ...

Page 82

... AND D30:F0 SECSTS Enable] [DPD] Master Cycle AND D31:F0 PCISTA D31:F0 PCICMD [DPED] [PER] Figure 7 details all the parity errors that the ICH5 can detect, along ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet To NMI# Output AND and OR Gating Logic OR NMI_EN [NMI_EN] ...

Page 83

... The ICH5 always drives 0s on bits AD[15:11] when converting Type 1 configurations cycles to Type 0 configuration cycles on PCI. 3. Address bits [10:1] are also be passed unchanged to PCI. 4. Address bit 0 is changed to 0. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet AD[31:11] during Address Phase of Type 0 Cycle on PCI 0000000000000000_00000b ...

Page 84

... EEPROM provides power-on initialization for hardware and software configuration parameters. From a software perspective, the integrated LAN controller appears to reside on the secondary side of the ICH5’s virtual PCI-to-PCI bridge (see assigned a different number, depending upon system configuration. 84 Section 5.1.2). This is typically Bus 1, but may be ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 85

... Backward compatible software with 82550, 82557, 82558 and 82559 • TCP/UDP checksum off load capabilities • Support for Intel’s Adaptive Technology 5.2.1 LAN Controller Architectural Overview Figure high-level block diagram of the ICH5 integrated LAN controller divided into four main subsystems: a Parallel subsystem, a FIFO subsystem, and the Carrier-Sense Multiple Access with Collision Detect (CSMA/CD) unit ...

Page 86

... LAN connection such as node address, as well as board manufacturing and configuration information. Both read and write accesses to the EEPROM are supported by the LAN controller. Information on the EEPROM interface is detailed in Section 5.2.3. 86 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 87

... EX 10/100 Mbps Ethernet LAN Connect components. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. The CSMA/CD unit can also be placed in a full-duplex mode that allows simultaneous transmission and reception of frames. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 87 ...

Page 88

... TRDY# signal and provides valid data on each data access. The LAN controller allows the processor to issue only one read cycle when it accesses the CSR, generating a disconnect by asserting the STOP# signal. The processor can insert wait-states by deasserting IRDY# when it is not ready. 88 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 89

... The LAN controller, when detecting system error, claims the cycle if it was the target of the transaction and continues the transaction as if the address was correct. Note: The LAN controller reports a system error for any error during an address phase, whether or not it is involved in the current transaction. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 89 ...

Page 90

... IRDY# to support zero wait-state burst cycles. The LAN controller also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signals completion of a data phase by deassertion and assertion of TRDY#. 90 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 91

... There are at least DWords of data space left in the system memory buffer. • The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1b. • The MWI Enable bit in the LAN Controller Configure command should is set to 1b. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 91 ...

Page 92

... LAN controller also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the LAN controller during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). 92 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 93

... PCI accesses to its configuration space and system wake-up events. The LAN controller retains link integrity and monitors the link for any wake-up events (e.g., wake-up packets or link status change). Following a wake-up event, the LAN controller asserts the PME# signal. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 93 ...

Page 94

... The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN controller PCI Configuration Space, MAC configuration, and memory structure are initialized while preserving the PME# signal and its context. 94 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 95

... The LAN controller reports a PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 95 ...

Page 96

... An EEPROM read instruction waveform is shown in Figure 9. Figure 9. 64-Word EEPROM Read Instruction Waveform EE_SHCLKK EE_CS EE_DIN EE_DOUT The LAN controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch, and Dh) of the EEPROM after the deassertion of Reset READ OP code ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 97

... This configuration only affects the LAN controller specific IA and not multicast, multi-IA or broadcast address filtering. The LAN controller does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 97 ...

Page 98

... Dx functionality plus: Force TCO Mode Config commands Read/Write PHY registers Note: For a complete description on various commands, see the Total Cost of Ownership (TCO) System Management Bus Interface Application Note (AP-430). 98 TCO Controller Functionality ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Table 32. ...

Page 99

... Note: The Force TCO is a destructive command. It causes the ICH5 to lose its memory structures, and during the Force TCO mode the ICH5 ignores any PCI accesses. Therefore highly recommended to use this command by the TCO controller at system emergency only. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description Section 7 ...

Page 100

... ASF controller compliant interface for retrieving info, sending alerts, and controlling timers. ICH5 provides an input and an output EEPROM interface. The EEPROM contains the LAN controller configuration and the ASF controller configuration/packet information. 100 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 101

... PET Compliant Packets - RMCP - Legacy Sensor Polling - ASF Sensor Polling - Remote Control Sensor Support • Advanced Features / Miscellaneous — SMBus 2.0 compliant — Optional reset extension logic (for use with a power-on reset) ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 101 ...

Page 102

... Sensor Configuration driver / application Note: Contact your Intel Field Representative for the Client ASF Software Development Kit (SDK) that includes additional documentation and a copy of the client ASF software drivers. Intel also provides an ASF Console SDK to add ASF support to a management console. ...

Page 103

... The ICH5 implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the ICH5 is shown in all of the signals that are shown as optional, but peripherals are not required to do so. Figure 10. LPC Interface Diagram ICH SUS_STAT# ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Figure PCI Bus PCI PCI CLK ...

Page 104

... Comment Single: 1 byte only Single: 1 byte only ® 1 byte only. Intel ICH5 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. See Note 1 below. 1 byte only. ICH5 breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. See Note 1 below. ...

Page 105

... ICH5 ignores those bits. Bits[1:0] are encoded as listed in Table 36. Transfer Size Bit Definition Bits[1:0] 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) Reserved. The Intel 10 master cycle drives this combination, the ICH5 may abort the transfer. 11 32-bit transfer (4 bytes) ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet shows the valid bit encodings ...

Page 106

... Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request 0000 deassertion and no more transfers desired for that channel. Short Wait: Part indicating wait-states. For bus master cycles, the Intel 0101 this encoding. Instead, the ICH5 uses the Long Wait encoding (see next encoding below). ...

Page 107

... ICH5 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern. • A peripheral drives an illegal address when performing bus master cycles. • A peripheral drives an invalid value. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Start ADDR TAR Sync 1 CYCTYPE ...

Page 108

... PCIRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol. 5.4.1.12 Configuration and Intel LPC I/F Decoders To allow the I/O cycles and memory mapped cycles the LPC interface, the ICH5 includes several decoders ...

Page 109

... DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register ® Figure 13. Intel ICH5 DMA Controller Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers ...

Page 110

... Similarly 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. 110 Low priority ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Section 9.2. ...

Page 111

... DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Current Byte/Word Count Register Bytes ...

Page 112

... Clear Mask Register This command clears the mask bits of all four channels, enabling them to accept DMA requests. I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7. 112 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 113

... DMA channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2=0,0,1,1] grants DMA channel 6 to the requesting device. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Figure 14. For example, the sequence [start, bit 0, bit 1, bit 2=0,1,0,0] grants ...

Page 114

... The DMA controller does a two cycle transfer (a load followed by a store) as opposed to the ISA "fly-by" cycle for PC/PCI DMA agents. The memory portion of the cycle generates a PCI memory read or memory write bus cycle, its address representing the selected memory. 114 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 115

... Table 43 Table 43. DMA I/O Cycle Width vs. BE[3:0]# BE[3:0]# 1110b 1100b NOTE: For verify cycles the value of the Byte Enables (BEs “don’t care.” ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet DMA I/O Address PCI Cycle Type 00h I/O Read/Write 04h ...

Page 116

... This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to self-arbitrate before sending the message. Figure 15. DMA Request Assertion through LDRQ# LCLK LDRQ# 116 Figure Start MSB LSB ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet 15, the peripheral uses the ACT Start ...

Page 117

... The peripheral indicates data ready through SYNC and transfers the first byte. — 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 117 ...

Page 118

... DMA request will remain active to the 8237 later time, the ICH5 will then come back with another START another transfer to the peripheral. 118 CYCTYPE CHANNEL SIZE etc. combination to initiate – – – ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 119

... To that end recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow with a bus mastering interface and not rely on the 8237. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 119 ...

Page 120

... A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format. 120 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 121

... The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Function Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed ...

Page 122

... If both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. 122 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 123

... Therefore, the term “high” indicates “active,” which means “low” originating PIRQ#. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Typical Interrupt Source ...

Page 124

... Table 47. Content of Interrupt Vector Byte Master, Slave Interrupt IRQ7,15 IRQ6,14 IRQ5,13 IRQ4,12 IRQ3,11 IRQ2,10 IRQ1,9 IRQ0,8 124 defines the IRR, ISR, and IMR. Description Bits [7:3] Bits [2:0] ICW2[7:3] ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet 111 110 101 100 011 010 001 000 ...

Page 125

... Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set Special mask mode is cleared and Status Read is set to IRR. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 125 ...

Page 126

... ICW4 The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set indicate that the controllers are operating in an Intel Architecture-based system. 5.8.3 Operation Command Words (OCW) These command words reprogram the Interrupt controller to operate in various interrupt modes. • ...

Page 127

... Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 127 ...

Page 128

... From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller. 128 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 129

... However, active low non-ISA interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The ICH5 receives the PIRQ input, like all of the other external sources, and routes it accordingly. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 129 ...

Page 130

... Option for SCI, TCO No Yes Option for SCI, TCO No Yes HPET #2, Option for SCI, TCO No Yes No No FERR# logic 1 Yes Yes Storage (IDE/SATA) Primary (legacy mode) 1 Yes Yes Storage (IDE/SATA) Secondary (legacy mode) ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Internal Modules ...

Page 131

... The interrupts associated with the PCI Message-based interrupt method must be set up for edge triggered mode, rather than level triggered, since the peripheral only does the write to indicate the edge. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Direct from Via PCI Pin ...

Page 132

... PCI-based interrupt messages precaution, the PRQ bit is not set if the XAPIC_EN bit is not set. Interrupt Message Register The PCI devices all write their message into the IRQ Pin Assertion Register, which is a memory- Mapped register located at the APIC base memory location + 20h. 132 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 133

... INIT. This means that in IA32/IA64 based platforms, Front Side Bus interrupt message format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used and is not supported. Only the hardware pin connection is supported by ICH5. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Table 49 and Table 50 for the address and data ...

Page 134

... Fixed 100 = NMI 10:8 001 = Lowest Priority 101 = INIT 010 = SMI/PMI 110 = Reserved 011 = Reserved 111 = ExtINT 7:0 Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt. 134 Description Description ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 135

... Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the ICH5 drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 135 ...

Page 136

... IRQ2 15 frames indicates that an active-high ISA interrupt is – – Next Mode Quiet Mode. Any SERIRQ device may initiate a Start Frame ® Continuous Mode. Only the host (Intel ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ICH5) may initiate a Start Frame ...

Page 137

... The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Clocks Past Start Frame 2 Ignored ...

Page 138

... The real-time clock interrupt is internally routed within the ICH5 both to the I/O APIC and the 8259 mapped to interrupt vector 8. This interrupt does not leave the ICH5, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. 138 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 139

... RTC CMOS array once the system is booted. The normal position would cause RTCRST pulled up through a weak pull-up resistor. their default state when RTCRST# is asserted. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description Table 53 shows which bits are set to ...

Page 140

... I/O space GEN_PMCON_3 D31:F0:A4h GEN_PMCON_3 D31:F0:A4h GEN_PMCON_3 D31:F0:A4h PM1_STS PMBase + 00h GPE0_EN PMBase + 2Ah GPE0_EN PMBase + 2Ah TCO1_STS TCOBase + 04h TCO2_STS TCOBase + 06h GEN_STS D31:F0:D4h PM1_EN PMBase + 02h GPE0_EN PMBase + 2Ah ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Location Bit(s) 11:8 1111b ...

Page 141

... When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high. Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes inactive. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description for OH Table 54 ...

Page 142

... RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT# signal to be generated to the processor. To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 143

... Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11). Difference Generally not used, but still supported by Intel Used for S1 State as well as preparation for entry to S3–S5 Also allows for THERM# based throttling (not via ACPI control methods). Should be connected to both processors ...

Page 144

... Table 57. Frequency Strap Behavior Based on Exit State State Exiting S1 There is no processor reset frequency strap logic is used. Based on PWROK going active, the Intel S3, S4, S5, the FREQ_STRAP field (D31:F0,Offset D4), the ICH5 drives the intended core frequency values A20M#, IGNNE#, NMI, and INTR. ...

Page 145

... Figure 17. Signal Strapping Processor A20M#, IGNNE#, INTR, NMI ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Sets High/Low Level for the Corresponding Signal NMI INTR IGNNE# A20M# CPURST# Host Controller INIT# Intel ® ICH5 PCIRST# Frequency Strap Register Mux Functional Description PWROK Si S 145 ...

Page 146

... ICH5 and System Power States Table 59 shows the power states defined for ICH5-based platforms. The state names generally match the corresponding ACPI states. Table 59. General Power States for Systems Using Intel State/ Substates Full On: Processor operating. Individual devices may be shut down to save power. The ...

Page 147

... For example, in going from S0 to S1, it may appear to pass through the G0/S0 states. These intermediate transitions and states are not listed in the table. Table 60. State Transition Rules for Intel Present State • Processor halt instruction • ...

Page 148

... GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen. Section details.) The interrupt remains asserted until all SCI ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Table 61. Note that when a Description 3.1. Although not specific power planes ...

Page 149

... TCO SMI — Change of the BIOSWP bit from TCO SMI — Write attempted to BIOS BIOS_RLS written to GBL_RLS written to Write to B2h register Periodic timer expires 64 ms timer expires ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet SCI SMI Additional Enables Yes Yes PME_EN=1 Yes Yes ...

Page 150

... Functional Description Table 62. Causes of SMI# and SCI (Sheet Cause Enhanced USB Legacy Support Event Enhanced USB Intel Specific Event UHCI USB Legacy logic Serial IRQ SMI reported Device monitors match address in its range SMBus Host Controller SMBus Slave SMI message SMBus SMBALERT# signal active ...

Page 151

... SLP_EN bit disables thermal throttling (since S1–S5 sleep state has higher priority). • The G3 state cannot be entered via any software mechanism. The G3 state indicates a complete loss of power. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 151 ...

Page 152

... Upon exit from the ICH5-controlled Sleep states, the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in 152 Comment ICH5 asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This Table ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet 64. ...

Page 153

... GPI[7:0] GPI[13:11], GPI8 The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the ICH5 are insignificant. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet States Can Wake From – (Note 1) Set RTC_EN bit in PM1_EN register – ...

Page 154

... Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#. Table 66. Transitions Due to Power Failure State at Power Failure S0, S1 154 AFTERG3_EN bit Transition When Power Returns ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet -standby goes high CC ...

Page 155

... If this bit is set, the ICH5 starts throttling using the ratio in the THRM_DTY field. When this bit is cleared the ICH5 stops throttling, unless the THRM# signal has been active for 2 seconds or if the THTL_EN bit is set (indicating that ACPI software is attempting throttling). ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 155 ...

Page 156

... SMI# or SCI generated (depending on SCI_EN) Wake Event. Transitions to S0 state. None Unconditional transition to S5 state. seconds ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet 67. Note that the transitions start as Comment Software typically initiates a Sleep state. Standard wakeup No effect since no power. Not latched nor detected. ...

Page 157

... RI# active, and the interrupt will be set Break event. Table 68. Transitions Due to RI# Signal Present State S0 S1–S5 Note: Filtering/Debounce on RI# will not be done in ICH5. Can be in modem or external. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Event RI_EN RI# Active X 0 ...

Page 158

... Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event state reached step #1, otherwise stay here. If the ICH5 never reaches S5, the ICH5 does not reboot until power is cycled. 158 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 159

... DMA Chan 1 base address high byte 1 DMA Chan 1 base count low byte 03h 2 2 DMA Chan 1 base count high byte ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Table 69 have read paths in ALT access mode. The access number field I Data Access Addr ...

Page 160

... CAh 2 CCh 2 CEh 2 D0h ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Restore Data Data Timer Counter 2 status, bits [5:0] Bit 7 = NMI Enable, Bits [6:0] = RTC Address 1 DMA Chan 5 base address low byte 2 DMA Chan 5 base address high byte 1 DMA Chan 5 base count low byte ...

Page 161

... The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done via the power supply external FETs to the motherboard. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Value Returned 000 000 ...

Page 162

... VRMPWRGD Signal This signal is connected to the processor’s VRM and is internally AND’d with the PWROK signal that comes from the system power supply. This saves the external AND gate found in desktop systems. 162 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 163

... Based on the above principles, the following measures are taken: • During S3 (STR), all signals attached to powered down planes are tri-stated or driven low. 5.13.12 Clock Generators The clock generator is expected to provide the frequencies shown in ® Table 72. Intel ICH5 Clock Inputs Clock Frequency Domain 100 MHz CLK100 ...

Page 164

... Allows software to hide a PCI device in terms of configuration space through the use of a device hide register (See • Integrated ASF Management support Note: Voltage ID from the processor can be read via GPI signals. 164 Section 8.1.26) ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 165

... FFh. If this occurs, the ICH5 sets the BAD_BIOS bit, which can then be reported via the Heartbeat and Event reporting using an external, Alert on LAN enabled LAN controller (See ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Section 5.14.2). Functional Description ...

Page 166

... Button again, the system should wake state and the processor should start executing the BIOS step 5 (power button press) is successful in waking the system, the ICH5 continues sending messages every heartbeat period until the BIOS clears the SECOND_TO_STS bit. (See note 2) 166 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 167

... This and the following rules/steps apply if the user intervention (power button press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog timer. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet timeout reset is attempted (using a button that pulses PWROK low or via ...

Page 168

... A spurious alert could occur in the following sequence: — The processor has initiated an alert using the SEND_NOW bit — During the alert, the THRM#, INTRUDER# or GPI11 changes state — The system then goes to a non-S0 state. 168 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 169

... ICH5 / 82801ER ICH5R Datasheet Comment 1 = This bit is set if the intruder detect bit is set (INTRD_DET). ® This bit is set if the Intel ICH5 THERM# input signal is asserted This bit is set if the processor failed to fetch its first instruction This bit is set when the TCO timer expires. ...

Page 170

... GPIO_USE_SEL bit 11 enables • Input active status read from GPE0_STS SMBALERT# Resume 3.3 V • Input active high/low set through GPI_INV ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Notes GNTA# pair. register bit 0. register bit 0. GNTB# pair (See note 4). register bit 1. ...

Page 171

... GPO20 Only Output GPIO21 Only Output GPIO22 Only Output GPIO23 Only ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Alternate Power Function Tolerant Well (Note 1) • Input active status read from GPE0_STS Unmuxed Resume 3.3 V • Input active high/low set through GPI_INV • ...

Page 172

... Input active status read from GP_LVL2 • TTL driver output • GPIO_USE_SEL bit 41 enables LDRQ1#. LDRQ1# Core 3.3 V • TTL driver output ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Notes register bit 24. bit 24. (D31:F0: Offset GPIOBASE+18h) bit 25 register bit 25 bit 25. ...

Page 173

... This makes these signals “level” triggered inputs. 5.15.3 SMI# and SCI Routing The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither. Note that a bit can be routed to either an SMI SCI, but not both. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Alternate Power Function Tolerant ...

Page 174

... The Command and Control Block registers are accessed differently depending on the decode mode, which is selected by the Programming Interface configuration register (Offset 09h). Note: The primary and secondary channels are controlled by separate bits, allowing one native mode and the other in legacy mode simultaneously. 174 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 175

... In native mode, the ICH5 does not decode the legacy ranges. The same offsets are used as in Table 75. However, the base addresses are selected using the PCI BARs, rather than fixed I/O locations. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Register Function Register Function (Read) ...

Page 176

... IDE transaction. This guarantees that the chip selects are deasserted for at least two PCI clocks between the two cycles. 176 Table 76. Note that bit 2 (16-bit I/O Startup IORDY Sample Recovery Time Latency Point (ISP) (RCT 2–5 1–4 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Shutdown Latency ...

Page 177

... If greater than the disk transfer request, the driver must terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal transfer completion. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 177 ...

Page 178

... PCI devices or the serial stream. Warning: In this mode, the ICH5 does not drive the PCI Interrupt associated with this function. That is only used in native mode. 178 Byte 2 Byte 1 Byte 0 Byte Count [15:1] ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Main Memory Memory Region o o ...

Page 179

... The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers terminate when the physical region described by the last PRD in the table has been completely transferred. The active bit in the Status Register is reset and the DDRQ signal is masked. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 179 ...

Page 180

... Specifics of the error have to be determined using bus-specific information. If the Error bit is not set, then the PRD's specified a smaller size than the IDE transfer size. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 181

... ICH5 / 82801ER ICH5R Datasheet Ultra ATA/33 Read Ultra ATA/33 Write Cycle Definition Cycle Definition STOP STOP DMARDY# STROBE STROBE DMARDY# Functional Description ® ® Intel ICH5 Intel ICH5 Primary Channel Secondary Signal Channel Signal PDIOW# SDIOW# PDIOR# SDIOR# PIORDY SIORDY 181 ...

Page 182

... ICH5 drives the CRC value onto the DD[15:0] signals then latched by the IDE device on deassertion of DDACK#. The IDE device compares the ICH5 CRC value to its own and reports an error if there is a mismatch. 182 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet writes, IDE – ...

Page 183

... This means that the ICH5 performs Mode 5 write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe is driven by the ATA/100 device, and the ICH5 supports reads at the maximum rate of 100 MB/s. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 183 ...

Page 184

... To block accesses to the native IDE ranges, software must use the generic power management control registers described in 184 177h, and 376h). If the IDE controller is in legacy mode and is using these – ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Section 9.10.14) contain control for (Section 9.10.13) are updated Section 9 ...

Page 185

... If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Section 11.1.32, provides the ability to share PCI functions. When sharing is ...

Page 186

... The Intel RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel RAID Technology implementation and provides the ability for a Intel RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel RAID Technology volume(s) attached to the Intel RAID controller. ...

Page 187

... Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Power Host = D0 Device = D0 ...

Page 188

... If the SATA controller is in legacy mode and is using – Section 9.8.9. Interrupt Register ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Section 9.10.14) contain control for (Section 9.10.13) are Wire-Mode Action MSI Action ...

Page 189

... Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1 and 2 only support 32-bit mode (See Section 17.5). ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet APIC Mapping IRQ0 IRQ2 IRQ8 ...

Page 190

... Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_VAL_SET_CNF bit 4. 4) Set the upper 32 bits of the Timer0 Comparator Value register 190 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 191

... If a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper 32-bits are always 0. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description SeeSection 5.9 ...

Page 192

... Reserved. These bits must be written as 0. QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer (Transfer Descriptor (Queue Head). This allows the Intel proper type of processing on the item after it is fetched Terminate (T) ...

Page 193

... When set to depth first, it informs the ICH5 to process the next transaction in the queue rather than starting a new queue Breadth first 1 = Depth first QH/TD Select (Q). This bit informs the Intel is another QH. This allows the ICH5 to perform the proper type of processing on the item after it is fetched Terminate (T) ...

Page 194

... Set software to enable the execution of a message transaction by the ICH5. 194 Description Interrupt After No Error Limit 1 Error 2 Errors 3 Errors Decrement Counter Error Yes Data Buffer Error Yes Stalled No Bit stuff Error 1 No Section ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Decrement Counter Yes 1 No Yes 5.19.2, Data Transfers to/from Main ...

Page 195

... It can be used by the 10:0 software to maintain data integrity. The value programmed in this register is encoded as n-1 (see Maximum Length field description in the TD Token). ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description Description 195 ...

Page 196

... Note that values from 500h to 7FEh are illegal and cause a consistency check failure. In the transmit case, the Intel fetches from host memory. In most cases, this is the number of bytes it will actually transmit. In rare cases, the ICH5 may be unable to access memory (e.g., due to excessive latency) in time to avoid underrunning the transmitter ...

Page 197

... QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link 1 pointer is another QH Terminate (T). This bit indicates to the Intel are active TDs in this queue, they are the last to be executed in this frame Pointer is valid (points TD Last QH (pointer is invalid). Table 88. Queue Element Link Pointer Bit Queue Element Link Pointer (QELP) ...

Page 198

... ICH5 fetches the next entry from the Frame List. If the ICH5 is not able to process all of the transfer descriptors during a given frame, those descriptors are retired by software without having been executed. 198 ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet ...

Page 199

... TD inactive 12. 11. Write the link pointer from the current TD into the element pointer field of the QH structure. If the Vf bit is set in the TD link pointer 12. Proceed to next entry. ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet Functional Description 199 ...

Page 200

... Host System Error, HC Process Error, and HC Halted bits Set USB Int bit Set USB Error Int bit 1 Set USB Error Int bit Set USB Int bit ® Intel 82801EB ICH5 / 82801ER ICH5R Datasheet TD Status Register Actions 1 Clear Active bit and set 1 ...

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