FW82801EB Intel, FW82801EB Datasheet - Page 392

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.6
392
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Enable Register. If the corresponding
_EN bit is set, then when the _STS bit get set, the ICH5 will generate a Wake Event. Once back in
an S0 state (or if already in an S0 state when the event occurs), the ICH5 will also generate an SCI
if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. There will be no SCI/SMI# or
wake event on THRMOR_STS since there is no corresponding _EN bit. None of these bits are
reset by CF9h write. All are reset by RSMRST#.
31:16
10:9
Bit
15
14
13
12
11
GPIn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
Reserved
USB4_STS — R/W.
0 = Disable
1 = Set by hardware and can be reset by writing a 1 to this bit position or a resume-well reset.
PME_B0_STS — R/W. This bit will be set to 1 by the Intel
PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal.
Additionally, if the PME_B0_EN bit is set, and the system is in an S0 state, then the setting of the
PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_STS bit is
set, and the system is in an S1–S4 state (or S5 state due to SLP_TYP and SLP_EN), then the
setting of the PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not
set) will be generated. If the system is in an S5 state due to power button override, then the
PME_B0_STS bit will not cause a wake event or SCI.
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
USB3_STS — R/W.
0 = Disable
1 = Set by hardware and can be reset by writing a 1 to this bit position or a resume-well reset.
PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set,
Reserved
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the
corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is
set:
This bit is set when USB UHCI controller #4 needs to cause a wake. Additionally if the
USB4_EN bit is set, the setting of the USB4_STS bit will generate a wake event.
This bit is set when USB UHCI controller #3 needs to cause a wake. Additionally if the
USB3_EN bit is set, the setting of the USB3_STS bit will generate a wake event.
and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or
SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or
S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will
generate a wake event, and an SCI will be generated. If the system is in an S5 state due to
power button override or a power failure, then PME_STS will not cause a wake event or SCI.
PMBASE + 28h
( ACPI GPE0_BLK )
00000000h
No
Resume
depending on the GPI_ROUT bits for the corresponding GPI.
Intel
Description
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 when any internal device with
32-bit
R/W, R/WC
ACPI