FW82801EB Intel, FW82801EB Datasheet - Page 330

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.22
330
GEN_CNTL — General Control Register
(LPC I/F — D31:F0)
Offset Address:
Default Value:
Lockable:
31:26
23:22
19:18
16:15
Bit
25
24
21
20
17
14
13
12
10
11
Reserved
REQ5#/GNT5# PC/PCI Protocol Select (PCPCIB_SEL) — R/W.
0 = The REQ5#/GNT5# pins function as a standard PCI REQ/GNT signal pair.
1 = PCI REQ5#/GNT5# signal pair will use the PC/PCI protocol as REQB#/GNTB. The
Hide ISA Bridge (HIDE_ISA) — R/W.
0 = The Intel
1 = Software sets this bit to 1 to disable configuration cycles from being claimed by a PCI-to-ISA
Reserved
Reserved
Reserved
Scratchpad — R/W. ICH5 does not perform any action on these bits.
HPET Address Enable (HPET_ADDR_EN ) — R/W.
0 = Disable
1 = Enable. ICH5 decodes the High-Precision Event Timers Memory Address Range selected by
HPET Address Select (HPET_ADDR_SEL) — R/W. This 2-bit field selects 1 of 4 possible memory
address ranges for the High-Precision Event Timers functionality. The encodings are:
Bits [16:15]Memory Address Range
00 FED0_0000h – FED0_03FFh
01 FED0_1000h – FED0_13FFh
10 FED0_2000h – FED0_23FFh
11 FED0_3000h – FED0_33FFh
Reserved
Coprocessor Error Enable (COPR_ERR_EN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = When FERR# is low, ICH5 generates IRQ13 internally and holds it until an I/O write to port
Keyboard IRQ1 Latch Enable (IRQ1LEN) — R/W.
0 = IRQ1 will bypass the latch.
1 = The active edge of IRQ1 will be latched and held until a port 60h read.
Mouse IRQ12 Latch Enable (IRQ12LEN) — R/W.
0 = IRQ12 will bypass the latch.
1 = The active edge of IRQ12 will be latched and held until a port 60h read.
Reserved
bits 16:15 below.
corresponding bits in the GPIO_USE_SEL register must also be set to a 0. If the
corresponding bits in the GPIO_USE_SEL register are set to a 1, the signals will be used as a
GPI and GPO.
bridge.
bridge. This will prevent the OS PCI PnP from getting confused by seeing two ISA bridges.
It is required for the ICH5 PCI address line AD22 to connect to the PCI-to-ISA bridge’s IDSEL
input. When this bit is set, the ICH5 will not assert AD22 during config cycles to the PCI-to-ISA
bridge.
F0h. It will also drive IGNNE# active.
D0h
00000004h
No
®
ICH5 will not prevent AD22 from asserting during config cycles to the PCI-to-ISA
–
D3h
Intel
Description
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, R/WO
32 bit
Core