FW82801EB Intel, FW82801EB Datasheet - Page 218

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.20.3.1.2
5.20.3.2
5.20.3.2.1
218
Asynchronous List Execution
Write Policies for Periodic DMA
The Periodic DMA engine performs writes for the following reasons:
NOTES:
The Asynchronous DMA engine contains buffering for two control structures (two transactions).
By implementing two entries, the EHC is able to pipeline the memory accesses for the next
transaction while executing the current transaction on the USB ports.
Read Policies for Asynchronous DMA
The Asynchronous DMA engine performs reads for the following structures.
The EHC Asynchronous DMA Engine (ADE) does not generate accesses to main memory unless
all four of the following conditions are met. (Note that the ADE may be active when the periodic
schedule is actively executed, unlike the description in the Enhanced Host Controller Interface
Specification for Universal Serial Bus, Revision 1.0; since the EHC contains independent DMA
engines, the ADE may perform memory accesses interleaved with the PDE accesses.)
1. The Periodic DMA Engine (PDE) will only generate writes after a transaction is executed on USB.
2. Status writes are always performed after In Data writes for the same transaction.
iTD Status Write
siTD Status Write
Interrupt Queue Head
Overlay
Interrupt Queue Head
Status Write
Interrupt qTD Status
Write
In Data
qTD
Queue Head
Out Data
•
•
•
•
Memory Structure
Structure
Memory
The HCHalted bit is 0 (memory space, offset 24h, bit 12). Software clears this bit indirectly by
setting the RUN/STOP bit to 1.
The Asynchronous Schedule Status bit is 1 (memory space, offset 24h, bit 14). Software sets
this bit indirectly by setting the Asynchronous Schedule Enable Bit to 1.
The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2).
The ADE is not sleeping due to the detection of an empty schedule. There is not one single bit
that indicates this state. However, the sleeping state is entered when the Queue Head with the
H bit set is encountered when the Reclamation bit in the USB 2.0 Status register is 0.
Size (DW)
Up to 129
13
17
(DWords)
Up to 257
Size
14
54
1
3
3
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
The Intel
requests based on the setting of the Read Request Max Length field.
Only the DWord that corresponds to the just-executed microframe’s
status is written. All bytes of the DWord are written.
DWords 0C:17h are written. IOC and Buffer Pointer fields are
re-written with the original value.
Only the 64-bit addressing format is supported. DWords 0C:43h are
written.
DWords 14:27h are written.
DWords 04:0Fh are written. PID Code, IOC, Buffer Pointers, and Alt.
Next qTD Pointers are re-written with the original value.
The Intel
chunks.
®
ICH5 breaks large read requests down in to smaller aligned read
®
ICH5 breaks data writes down into 16 DWord aligned
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
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