FW82801EB Intel, FW82801EB Datasheet - Page 10

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Contents
10
5.17
5.18
5.19
5.16.2 Bus Master Function............................................................................................ 177
5.16.3 Ultra ATA/33 Protocol .......................................................................................... 181
5.16.4 Ultra ATA/66 Protocol .......................................................................................... 183
5.16.5 Ultra ATA/100 Protocol ........................................................................................ 183
5.16.6 Ultra ATA/33/66/100 Timing ................................................................................ 183
5.16.7 IDE Swap Bay...................................................................................................... 184
5.16.8 SMI Trapping (APM) ............................................................................................ 184
SATA Host Controller (D31:F2) ........................................................................................ 185
5.17.1 Theory of Operation............................................................................................. 185
5.17.2 Hot Swap Operation ............................................................................................ 186
5.17.3 Intel
5.17.4 Power Management Operation............................................................................ 186
5.17.5 SATA Interrupts ................................................................................................... 188
High-Precision Event Timers ............................................................................................ 188
5.18.1 Timer Accuracy.................................................................................................... 189
5.18.2 Interrupt Mapping................................................................................................. 189
5.18.3 Periodic vs. Non-Periodic Modes......................................................................... 189
5.18.4 Enabling the Timers............................................................................................. 191
5.18.5 Interrupt Levels .................................................................................................... 191
5.18.6 Handling Interrupts .............................................................................................. 191
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors...................................... 191
USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ..................................................... 192
5.19.1 Data Structures in Main Memory ......................................................................... 192
5.19.2 Data Transfers to/from Main Memory .................................................................. 198
5.16.1.2 IDE Legacy Mode and Native Mode .................................................... 175
5.16.1.3 PIO IDE Timing Modes ........................................................................ 176
5.16.1.4 IORDY Masking ................................................................................... 176
5.16.1.5 PIO 32-Bit IDE Data Port Accesses..................................................... 176
5.16.1.6 PIO IDE Data Port Prefetching and Posting ........................................ 177
5.16.2.1 Physical Region Descriptor Format ..................................................... 177
5.16.2.2 Line Buffer............................................................................................ 178
5.16.2.3 Bus Master IDE Timings ...................................................................... 178
5.16.2.4 Interrupts.............................................................................................. 178
5.16.2.5 Bus Master IDE Operation ................................................................... 179
5.16.2.6 Error Conditions ................................................................................... 180
5.16.2.7 8237-Like Protocol ............................................................................... 180
5.16.3.1 Signal Descriptions .............................................................................. 181
5.16.3.2 Operation ............................................................................................. 182
5.16.3.3 CRC Calculation .................................................................................. 182
5.17.1.1 Standard ATA Emulation ..................................................................... 185
5.17.1.2 48-Bit LBA Operation ........................................................................... 185
5.17.3.1 Intel
5.17.4.1 Power State Mappings......................................................................... 186
5.17.4.2 Power State Transitions....................................................................... 187
5.17.4.3 SMI Trapping (APM) ............................................................................ 188
5.19.1.1 Frame List Pointer................................................................................ 192
5.19.1.2 Transfer Descriptor (TD) ...................................................................... 193
5.19.1.3 Queue Head (QH)................................................................................ 197
5.19.2.1 Executing the Schedule ....................................................................... 198
5.19.2.2 Processing Transfer Descriptors.......................................................... 199
5.19.2.3 Command Register, Status Register,
®
RAID Technology Configuration (Intel
and TD Status Bit Interaction ............................................................... 200
®
RAID Technology Option ROM.................................................. 186
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
82801ER ICH5R Only)................ 186