FW82801EB Intel, FW82801EB Datasheet - Page 412

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.12.5
9.12.6
412
GPI_INV—GPIO Signal Invert Register
Offset Address:
Default Value:
Lockable:
GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address:
Default Value:
Lockable:
31:16
15:8
31:0
Bit
7:0
Bit
Reserved
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least 2 PCI clocks
to ensure detection by the Intel
at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding
GPIO is programmed as an output. These bits correspond to GPIO that are in the Resume well, and
will be reset to their default values by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when the ICH5 detects the state of the input pin to be
1 = The corresponding GPI_STS bit is set when the ICH5 detects the state of the input pin to be
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least 2 PCI clocks
to ensure detection by the ICH5. The setting of these bits will have no effect if the corresponding
GPIO is programmed as an output. These bits correspond to GPIO that are in the Core well, and will
be reset to their default values by PCIRST#.
0 = The corresponding GPI_STS bit is set when the ICH5 detects the state of the input pin to be
1 = The corresponding GPI_STS bit is set when the ICH5 detects the state of the input pin to be
GPIO_USE_SEL2[49:48, 41:40]— R/W. Each bit in this register enables the corresponding GPIO (if
it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as
their native function rather than as a GPIO. After just a PCIRST#, the GPIO in the core well are
configured as their native function.
1. The following bits are not implemented because there is no corresponding GPIO: 31:18, 16:10,
2. The following bits are always 1 because they are unmuxed: 2:0.
3. If GPIOn does not exist, then the bit in this register will always read as 0 and writes will have no
7:3.
effect.
high.
low.
high.
low.
GPIOBASE +2Ch
00000000h
No
GPIOBASE +30h
00000007h
No
®
ICH5. In the S3, S4 or S5 states the input signal must be active for
Description
Intel
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32-bit
See bit description
R/W
32-bit
Core