FW82801EB Intel, FW82801EB Datasheet - Page 311

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

8.1.24
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
BRIDGE_CNT—Bridge Control Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:12
Bit
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Discard Timer SERR# Enable (DTSE) — R/W. The Intel
transaction on the secondary interface as an error (see bit 10 in this register). Therefore, this bit has
no effect on the hardware. It is implemented as read/write for software compatibility.
Discard Timer Status (DTS) — RO. Hardwired to 0. ICH5 only performs delayed transactions on
behalf of PCI memory reads to prefetchable memory.
Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI clock cycles
that the ICH5 waits for an initiator on PCI to repeat a delayed transaction request. The counter starts
once the delayed transaction completion is at the head of the queue. If the master has not repeated
the transaction at least once before the counter expires, the ICH5 discards the transaction from its
queue.
0 = The PCI master timeout value is between 2
1 = The PCI master timeout value is between 2
Primary Discard Timer (PDT ) — R/W. This bit is R/W for software compatibility only.
Fast Back to Back Enable — RO. Hardwired to 0. The PCI logic will not generate fast back-to-back
cycles on the PCI bus.
Secondary Bus Reset — RO. hardwired to 0. The ICH5 does not follow the PCI-to-PCI bridge reset
scheme; Software-controlled resets are implemented in the PCI-LPC device.
Master Abort Mode — R/W. This bit is R/W for software compatibility and has no affect on ICH5
behavior.
VGA 16-Bit Decode. This bit does not have any functionality relative to address decodes because
the ICH5 forwards the cycles to PCI, independent of the decode. Writes of 1 have no impact other
than to force the bit to 1. Writes of 0 have no impact other than to force the bit to 0. Reads to this bit
will return the previously written value (or 0 if no writes since reset).
VGA Enable — R/W.
0 = No VGA device on PCI.
1 = Indicates that the VGA device is on PCI. Therefore, the PCI to hub interface decoder will not
ISA Enable — R/W. The ICH5 ignores this bit. However, this bit is read/write for software
compatibility. Since the ICH5 forwards all I/O cycles that are not in the USB, AC ’97, or IDE ranges to
PCI, this bit would have no effect.
SERR# Enable — R/W.
0 = Disable
1 = Enable. If this bit is set AND bit 8 in PCICMD register (D30:F0 Offset 04h) is also set, the ICH5
NOTE: The internal SERR# will be generated only if the SERR_EN (D30:F0:04h bit 8) bit is also
Parity Error Response Enable — R/W.
0 = Disable
1 = Enable the hub interface to PCI bridge for parity error detection and reporting on the PCI bus.
accept memory cycles in the range A0000h–BFFFFh. Note that the ICH5 will never take I/O
cycles in the VGA range from PCI.
will set the SSE bit in PCISTS register (D30:F0, offset 06h, bit 14) and also generate an NMI (or
SMI# if NMI routed to SMI) when the SERR# signal is asserted.
set.
3E
0000h
–
3Fh
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Attribute:
Size:
15
10
and 2
and 2
16
11
®
ICH5 does not treat a discarded delayed
PCI clocks
PCI clocks
R/W, RO
16 bits
311