FW82801EB Intel, FW82801EB Datasheet - Page 549

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

15.2.1
Intel
®
Table 170. Native Audio Bus Master Control Registers (Sheet 2 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Internal reset as a result of D3
registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well registers will not be
reset by the D3
Core well registers and bits not reset by the D3
Resume well registers and bits will not be reset by the D3
x_BDBAR—Buffer Descriptor Base Address Register
(Audio—D31:F5)
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single 32-bit read from address offset
00h. Reads across DWord boundaries are not supported.
•
•
•
•
Offset
31:3
6Ah
6Bh
Bit
2:0
64h
65h
66h
68h
80h
offset 2Ch
offset 30h
offset 34h – Codec Access Semaphore Register (CAS)
offset 30h
Buffer Descriptor Base Address[31:3] — R/W. These bits represent address bits 31:3. The data
should be aligned on 8-byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
Hardwired to 0.
Mnemonic
SP_PICB
SP_CIV
SP_PIV
SP_CR
SP_LVI
SP_SR
–
–
SDM
–
HOT
33h – bits [29,15,11:10,0] Global Status (GLOB_STA)
33h – bits [17:16] Global Status (GLOB_STA)
2Fh – bits 6:0 Global Control (GLOB_CNT)
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
00000000h
No
to D0 transition.
S/PDIF Current Index Value
S/PDIF Last Valid Index
S/PDIF Status
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
S/PDIF Control
SData_IN Map
HOT
to D0 transition will reset all the core well registers except the
Name
HOT
AC ’97 Audio Controller Registers (D31:F5)
Description
Size:
Power Well:
to D0 transition:
HOT
to D0 transition:
Default
0001h
0000h
00h
00h
00h
00h
00h
R/W
32 bits
Core
R/W, R/W (special)
R/WC, RO
R/W, RO
Access
R/W
RO
RO
RO
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