FW82801EB Intel, FW82801EB Datasheet - Page 408

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.11.8
9.11.9
9.11.10
408
TCO2_CNT—TCO2 Control Register
I/O Address:
Default Value:
Lockable:
TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address:
Default Value:
Lockable:
TCO_WDSTS—TCO Watchdog Status Register
Offset Address:
Default Value:
Power Well:
15:4
Bit
2:1
Bit
7:0
Bit
7:0
3
0
Reserved
GPIO11_ALERT_DISABLE — R/W. At reset (via RSMRST# asserted) this bit is set and GPIO11
alerts are disabled.
0 = Enable
1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus slave.
INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes active.
00 = No interrupt or SMI#
01 = Interrupt (as selected by TCO_INT_SEL).
10 = SMI
11 = Reserved
Reserved
TCO_MESSAGE[ n ] — R/W. The value written into this register will be sent out via the SMLINK
interface in the MESSAGE field of the Alert On LAN message. BIOS can write to this register to
indicate its boot progress which can be monitored externally.
On LAN message on the SMLINK interface. It can be used by the BIOS or system management
software to indicate more details on the boot progress. This register will be reset to the default of
00h based on RSMRST# (but not PCI reset).
Watchdog Status (WDSTATUS) — R/W. The value written to this register will be sent in the Alert
TCOBASE +0Ah
0008h
No
TCOBASE +0Ch (Message 1) Attribute:
TCOBASE +0Dh (Message 2)
00h
No
TCOBASE + 0Eh
00h
Resume
Description
Intel
Description
Description
Attribute:
Size:
Power Well:
Size:
Power Well:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16-bit
Resume
R/W
8-bit
Resume
R/W
8 bits