FW82801EB Intel, FW82801EB Datasheet - Page 231

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.21
5.21.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Host Controller
SMBus Controller (D31:F3)
The ICH5 provides an SMBus 2.0 compliant Host controller as well as an SMBus Slave Interface.
The Host controller provides a mechanism for the processor to initiate communications with
SMBus peripherals (slaves). The ICH5 is also capable of operating in a mode in which it can
communicate with I
The ICH5 can perform SMBus messages with either packet error checking (PEC) enabled or
disabled. The actual PEC calculation and checking is performed in hardware by the ICH5.
The Slave Interface allows an external master to read from or write to the ICH5. Write cycles can
be used to cause certain events or pass messages, and the read cycles can be used to determine the
state of various status bits. The ICH5’s internal Host controller cannot access the ICH5’s internal
Slave Interface.
The ICH5 SMBus logic exists in Device 31:Function 3 configuration space, and consists of a
transmit data path, and host controller. The transmit data path provides the data flow logic needed
to implement the seven different SMBus command protocols and is controlled by the host
controller. The ICH5 SMBus controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller
commands through software, except for the new Host Notify command (which is actually a
received message).
The programming model of the host controller is combined into two portions: a PCI configuration
portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is
done via the PCI configuration space. Real-time programming of the Host interface is done in
system I/O space.
The SMBus Host controller is used to send commands to other SMBus slave devices. Software sets
up the host controller with an address, command, and, for writes, data and optional PEC; and then
tells the controller to start. When the controller has finished transmitting data on writes, or
receiving data on reads, it generates an SMI# or interrupt, if enabled.
The host controller supports 8 command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte,
Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write–Block Read
Process Call, and Host Notify.
The SMBus Host controller requires that the various data and command fields be setup for the type
of command to be sent. When software sets the START bit, the SMBus Host controller performs
the requested transaction, and interrupts the processor (or generate an SMI#) when the transaction
is completed. Once a START command has been issued, the values of the “active registers” (Host
Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read
until the interrupt status bit (INTR) has been set (indicating the completion of the command). Any
register values needed for computation purposes should be saved prior to issuing of a new
command, as the SMBus Host controller updates all registers while completing the new command.
Using the SMB host controller to send commands to the ICH5’s SMB slave port is supported. The
ICH5 is fully compliant with the System Management Bus (SMBus) Specification, Version 2.0.
Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The
SMLink and SMBus signals should not be tied together externally.
2
C compatible devices.
Functional Description
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